JPH03220917A - A/d converter circuit - Google Patents

Abstract

PURPOSE:To implement one-input A/D conversion and plural-input A/D conversion efficiently by determining the control mode of a sequence control section applying time series A/D conversion based on a content of a control register capable of write from outside. CONSTITUTION:Plural kinds of control modes by a sequence control section 20 relating optional one input and optional plural inputs of A/D conversion are predetermined through the constitution of 1st multiplexers (12-1)-(12-n), sample-hold circuit sections (10-10)-(10-n), a 2nd multiplexer 14, an A/D converter section 16 and registers (18-1)-(18-n). Thus, when a control code of a desired control mode is written externally to a control register 22 externally to give a start signal, one or plural inputs of A/D conversion according to the content of the control register 22 is implemented efficiently.

Description

[Detailed Description of the Invention] [Summary] A that converts an analog input signal into a digital signal and outputs it.
Regarding the D conversion circuit, the purpose is to efficiently perform AD conversion of one input and AD conversion of multiple inputs.After sampling and holding multiple inputs in parallel, they are selected sequentially by a multiplexer and AD converted, and then installed in parallel. The control mode of the sequence control unit that performs this AD conversion operation in time series is determined by the contents of the externally writable control register.

[Industrial Application Field] The present invention relates to an AD conversion circuit that converts an analog input signal into a digital signal and outputs the digital signal.

An AD conversion circuit generally consists of a sample hold section, an AD conversion section, and a register.
(2) When AD converting an input and AD converting a plurality of inputs selectively, an AD conversion circuit for one input is provided for each of a plurality of inputs, and one or more AD conversion circuits are selectively operated.

However, providing an AD conversion circuit for one input for each multiple inputs increases the circuit scale and is not economical.However, AD conversion for one input and AD conversion for multiple inputs is efficient without sacrificing economic efficiency. An AD conversion circuit that can do this is desired.

[Prior Art] Conventionally, an AD conversion circuit capable of selectively performing AD conversion of one input and AD conversion of multiple inputs consists of a sample hold section, an AD conversion section, and a register for each of a plurality of input channels. An AD conversion circuit for one input is provided, and AD conversion of one input is performed by operating one of the circuits, and AD conversion of multiple inputs can be performed by operating a plurality of circuits at the same time.

[Problem to be solved by the invention] However, the AD for one input for each of multiple input channels is
Conventional circuits provided with conversion circuits have the problem that the circuit scale increases depending on the number of input channels, resulting in a significant decrease in economic efficiency.

In order to solve this problem, it is possible to sequentially select multiple input channels using a multiplexer and apply them to a single-input AD conversion circuit, but this would cause a time lag in the sampling of multiple inputs, resulting in simultaneous AD conversion of multiple inputs. cannot satisfy that requirement.

The present invention has been made in view of such conventional problems, and an object of the present invention is to provide an AD conversion circuit that can efficiently perform AD conversion of one input and AD conversion of multiple inputs without impairing economic efficiency. shall be.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, first, a plurality of sample and hold units 10-1 to 10 corresponding to the number of inputs to be simultaneously AD converted.
-n is provided. This sample hold section 10-1~
10-2, a plurality of first multiplexers 1 select and input one of at least two analog input signals;
2-1 to 12-n are provided.

The respective outputs of the plurality of sample and hold sections 10-1 to 10-n are sequentially selected by the second multiplexer 14 and provided to the AD conversion section 16 which converts the analog signal into a digital signal. Following the AD converter 16 are a plurality of registers 18-1.
- 18-n are provided to sequentially store the digital signals from the AD converter 16, and then read them out and output them to the outside.

Such first multiplexers 12-1 to 12-n and sample and hold units 10-1 to 10-n.

A sequence control section 20 is provided that controls the second multiplexer 14, the AD conversion section 16, and the registers 18-1 to 18-n in a time-series manner by starting operations based on an external start signal. Furthermore, the control mode of AD conversion by the sequence control unit 20 is determined by the contents (control code) of the control register 20 that can be rewritten from the outside.

Further, a busy control circuit 24 is provided which outputs a busy signal indicating that the sequence control circuit 20 is in the middle of an AD conversion operation.

[Function] According to the AD conversion circuit of the present invention having such a configuration, the first multiplexer 12-1 to 12-n1 sample hold section 10-1 to 10-n% second multiplexer 14
, the configuration of the AD conversion unit 16 and the registers 18-1 to 18-n, a plurality of types of control modes by the sequence control unit 20 regarding AD conversion of arbitrary one input and arbitrary plural inputs are predetermined, and the control register 22 When a control code of a desired control mode is written externally into the control register 22 and a start signal is applied, AD conversion of one input or multiple inputs can be performed according to the contents of the control register 22 at that time.

Further, although sample-hold sections and registers are required for the number of inputs that require simultaneous conversion, only one circuit is required for the AD conversion section, which occupies a large proportion of the entire circuit, making it possible to achieve high economic efficiency.

Furthermore, the external device that started the AD conversion circuit can perform other processing until the busy signal returns from active to negative deep to indicate the completion of AD conversion, and is not restricted by the conversion time of the AD conversion circuit. do not have.

Embodiment FIG. 2 is a block diagram showing an embodiment of the present invention.

In FIG. 2, 100 is an AD conversion circuit of the present invention, which has four channel inputs A and B in this embodiment.
, C, and D, a case is taken as an example in which arbitrary one input or two inputs are simultaneously AD converted.

The AD conversion circuit 100 receives two channel inputs A at the same time.
Sample and hold circuit 10-1.1 from D conversion
0-2 is provided. Sample hold circuit 10-1.
The input stage of 10-2 includes a multiplexer (first multiplexer) 12-1. 12-2 is provided. The multiplexer 12-1 selectively outputs either input A or B, and the multiplexer 12-2 selectively outputs either input C or D.

The outputs of the sample and hold circuits 10-1 and 10-2 are input to a multiplexer (second multiplexer) 14, and one of them is selectively output. The output of the multiplexer 14 is given to an AD converter 16 and converted into, for example, an 8-bit digital signal. Following the AD converter 16, there are two registers 1 corresponding to the number of inputs to be simultaneously AD converted (2).
A multiplexer 12-1.12-2, a sample hold circuit 10-1.10-2, A sequence control circuit 20 is provided for operating the multiplexer 14, the AD converter 16, and the registers 18-1, 18-2 in time series to perform AD conversion.

The sequence control circuit 20 receives a start signal from an externally provided microprocessor 26 and starts a control operation for AD conversion. The control mode of the AD conversion circuit 100 by the sequence control circuit 20 is determined by the contents of the control register 22. A control code that determines a control mode is written into the control register 22 by an external microprocessor 26 via a bus 28, and upon receiving the start signal, the sequence control circuit 20 selects a control mode according to the contents of the control register 22 at that time. The AD conversion circuit 100 operates in a time-series manner.

Further, the control signal of the sequence control circuit 20 is given to a busy control circuit 24, and the busy control circuit 24 keeps the microprocessor 26 busy until the sequence control circuit 20 completes a series of time-series AD conversion operations. Make the signal active.

Here, the control modes of the AD conversion circuit 100 by the sequence control circuit 20 determined by the contents of the control register 22 are predetermined as modes 1 to 6, as shown in FIG. The control code set to 22 is 000-101. The content according to each control mode is that for modes 1 and 2, two inputs A, C, B, and D are simultaneously sampled and AD converted sequentially, and for the remaining modes 3 to 6, inputs A, B,
C.

A control mode is entered in which AD conversion is performed after sampling only D.

Next, referring to the operation timing chart of FIG. 4, description will first be given of mode 1 of FIG. 3, that is, the operation of simultaneously sampling inputs A and C and sequentially AD converting them.

First, the microprocessor 26 controls the control register 2.
2, a control code r instructs analog input signals A and C to be sampled simultaneously and then to be AD converted continuously.
Write 000J. When the microprocessor 26 activates the start signal, the sequence control circuit 2
0 gives a control output to the busy control circuit 24, activates the busy signal, and also controls the control register 2 at that time.
The input A of the multiplexer 12-1 is selected according to the content r000J of 2, and the input C of the multiplexer 12-2 is selected at the same time, and the sample and hold circuits 10-1 and 10-2 are selected.
The sampling operations of the sample and hold circuits 10-1. and 10-1. are started simultaneously, and after a certain period of time required for sampling has elapsed, the sample and hold circuits 10-1.
The sampling operation 10-2 is completed and the output is held.

Next, under the control of the multiplexer 14, the sample and hold circuit 10-1 side is selected and applied to the ADD converter 16, and the ADD
The D converter 16 is caused to start AD conversion. After a certain period of time required for AD conversion has elapsed, the conversion result from the ADD converter 16 is stored in the register 18-1, and the AD conversion on the input A side is completed. Next, sample and hold circuit 1 is connected to multiplexer 14.
Select the 0-2 side and cause the ADD converter 16 to start AD conversion. After a certain period of time required for AD conversion has elapsed, the conversion result of the ADD converter 16 is stored in the register 18-2.

As a result, the AD conversion result of input A is stored in register 18-1, and the AD conversion result of input C is stored in register 18-2. When such AD conversion is completed, the sequence control circuit 20 releases the control signal to the busy control circuit 24 and returns the busy signal to negative. The microprocessor 26 monitors the busy signal from the busy control circuit 24, and when it detects that the busy signal changes from active to negative, it reads the contents of register 18-1 via bus 28 and then reads the contents of register 18-1.
-2 is read and the series of AD conversion processing is completed.

Next, AD with only analog input A shown in mode 3 in Figure 4.
The conversion operation will be explained.

The microprocessor 26 writes a control code "010" instructing to sample and AD convert only the analog input signal A to the control register 22, and when the microprocessor 26 activates the start signal, the sequence control circuit 20 becomes a busy control circuit. 24 to make the busy signal active, and at the same time, according to the content r010J of the control register 22, input is first selected by the multiplexer 12-1 and the sampling operation of the sample-and-hold circuit 10-1 is started. After a certain period of time required for sampling has elapsed, the sampling operation of the sample and hold circuit 10-1 is terminated and the output is held. Next, the multiplexer 14 selects the sample hold circuit 10=1 side, and the AD converter 16 starts AD conversion. After a certain period of time required for AD conversion has elapsed, the conversion results of AD conversion earthwork 6 etc. are stored in register 18-.
Store in 1. As a result, register 18-1 has input A.
This means that the AD conversion results are stored. Here, the sequence control circuit 20 turns off the control signal to the busy control circuit 24 and returns the busy signal to negative. The microprocessor 26 indicates that the busy signal has gone negative.
When detected, the microprocessor 26 reads the contents of the register 18-1 via the bus 28, and ends the series of processing.

Similarly, the microprocessor 26 rewrites the contents of the control register 22 to perform mode 2 (control code 001) in which inputs B and D are sampled simultaneously and AD converted continuously, and sampling and AD conversion of only input B is performed. The same procedure is performed for mode 4 (control code 011), mode 5 (control code 100) that performs sampling and AD conversion of only input C, and mode 6 (control code 101) that performs sampling and AD conversion of only input C. be able to.

Here, as is clear from the operation timing chart in FIG. 4, the processing time T2 required for AD conversion of one input in modes 3 to 6 is the processing time T1 required for AD conversion of two inputs in modes 1 and 2. , second AD in motos 1 and 2
This time excludes conversion and register storage. As a result, 2
The processing time for AD conversion of one input can be reduced to approximately half that of AD conversion of input.

On the other hand, in the case of two inputs, the processing time T1 is approximately twice that of one input.
However, the microprocessor 26 is connected to the AD conversion circuit 1.
It is not restricted to the processing time of 00.

That is, when the microprocessor 26 makes the start signal active, the busy signal from the busy control circuit 24 becomes active while AD conversion processing is being performed, and while the busy signal is in the active state, the microprocessor 26 This is because the register 18-1, 18-2 can perform other control processing, and the registers 18-1 and 18-2 can be read upon detecting that the busy signal has returned to the negative state. Therefore, the A of the microprocessor 26
The time loss and software load required for D conversion processing are reduced, and the utilization efficiency of the microprocessor 26 can be increased.

Although the above embodiment takes as an example an AD conversion circuit that enables AD conversion of two inputs by providing two sample and hold circuits, the present invention is not limited to this, and can perform AD conversion at the same time. It is possible to freely construct a circuit configuration corresponding to the number of inputs to be performed.

Furthermore, in the above embodiment, the microprocessor 26 starts AD conversion after writing the code indicating the AD conversion mode to the control register 22, but the writing to the control register 22 and the start of AD conversion are performed at the same timing. You can also do it with

[Effects of the Invention] As described above, according to the present invention, AD conversion of any one input among multiple inputs or any plurality of inputs can be efficiently performed as necessary by setting a control code from the outside. be able to. In addition, sample and hold sections and registers are required for the number of inputs that require simultaneous conversion, but
The AD conversion section, which occupies a large proportion of the entire circuit, only needs to be one circuit, making it possible to achieve high economic efficiency.

Furthermore, since a signal (busy signal) indicating the start and end of AD conversion processing is output to the outside, the external device is not restricted by the processing time on the AD conversion circuit side, and can be used at any timing after the processing is completed. This method has the advantage that external control processing is not restricted to AD conversion processing.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention; FIG. 2 is a configuration diagram of an embodiment of the present invention; FIG. 3 is a diagram illustrating a control mode of the present invention; FIG. 4 is an operation timing chart of the present invention. In the figure, 0-110-2.10-n + sample hold section (circuit) 2-112-212-n: first multiplexer 4:
2nd multiplexer 6: AD conversion section (AD converter) 8-1.18-218-n: Register 20 sequence control section (circuit) 22: Control register (control register) 24: Busy control circuit 26 2 microprocessor 28 : Bus 100: AD conversion circuit

Claims (2)

[Claims] (1) A plurality of sample hold sections (10-1 to 10-n) that sample and hold analog input signals; each of the plurality of sample hold sections (10-1 to 10-n) has at least two A plurality of first multiplexers (12-1 to 1) that select and input one of the analog input signals;
2-n); the plurality of sample hold units (10-1 to 10-n);
a second multiplexer (14) that selects one of the outputs; an AD converter (16) that converts the output signal of the second multiplexer (14) into a digital signal; and a converted signal of the AD converter (16). a plurality of registers (18-1 to 18-n) storing; the first multiplexer (12-1 to 12-n); a sample hold unit (10
-1 to 10-n), second multiplexer (14), AD
a sequence control unit (20) that controls the conversion unit (16) and the registers (18-1 to 18-n) in a time-series manner by starting the operation based on an external start signal; a control register (20) that determines the control mode of the sequence control unit (20) according to the control code;
22) and ; An AD conversion circuit characterized in that it selectively performs AD conversion for one input and AD conversion for multiple inputs depending on the contents of the control code of the control register (22). (2) A according to claim 1, further comprising a busy control circuit (24) that outputs a busy signal indicating that the sequence control circuit (20) is performing an AD conversion operation to the outside.
D conversion circuit.