JPS5880879A - Obtaining method for collision ionization coefficient ratio by junction of different semiconductor - Google Patents

Obtaining method for collision ionization coefficient ratio by junction of different semiconductor

Info

Publication number
JPS5880879A
JPS5880879A JP56179438A JP17943881A JPS5880879A JP S5880879 A JPS5880879 A JP S5880879A JP 56179438 A JP56179438 A JP 56179438A JP 17943881 A JP17943881 A JP 17943881A JP S5880879 A JPS5880879 A JP S5880879A
Authority
JP
Japan
Prior art keywords
semiconductor
layer
coefficient ratio
ionization coefficient
semiconductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56179438A
Other languages
Japanese (ja)
Other versions
JPH0526356B2 (en
Inventor
Hiroyuki Sakaki
裕之 榊
Tomonori Tagami
知紀 田上
Hideaki Nojiri
英章 野尻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP56179438A priority Critical patent/JPS5880879A/en
Priority to US06/437,627 priority patent/US4553317A/en
Priority to DE19823241176 priority patent/DE3241176A1/en
Publication of JPS5880879A publication Critical patent/JPS5880879A/en
Publication of JPH0526356B2 publication Critical patent/JPH0526356B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To obtain a collision ionization coefficient ratio even by the junction of semiconductros of different types by laminating the semiconductors of different types, and setting both electrons and holes to move in a layer of the semiconductors of different ytpes isolated in space when both are flowed in parallel with the layer. CONSTITUTION:At least three layers and more of an alternative layer of semiconductors A and B to satisfy xA<xB, xA+EgA<xB+EgB, where xA represents electron affinity of the semiconductor B, EgA forbidden band width of the semiconductor A, XB electron affinity of the semiconductor B and EgB forbidden band width of the semiconductor B, and an electric field is applied in parallel with the layer. Further, an acceptor impurity is introduced to the semiconductor A, and a doner impurity is introduced to the semiconductor B, thereby generating an electric field vertical to the layer and accelerating the holes to flow into the layer of the semiconductor A and the electrons to flow into the layer of the semiconductor B.

Description

【発明の詳細な説明】 本発明は、受光素子、マイクロ波発振素子等のなだれ増
倍を用いた半導体素子において、電子と正孔の電離係数
比を人為的に得る方法Ellするものモある。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for artificially obtaining the ionization coefficient ratio of electrons and holes in semiconductor devices using avalanche multiplication, such as light receiving devices and microwave oscillation devices.

従来、衝突電離によるなだれ増倍を用いた素子とし【は
、インバットダイオード、アバランシェ・フォト・ダイ
オード等が知られている。そして、これ等の素子の応答
速度、雑音、感度等の動作特性は、なだれ増倍により生
じる電子と正孔の電離係数比(1/II K依存するこ
とが分つ【いる。この様な衡突電離現象の生ずる物質と
して現在知られている物質は、極く限られた□半導体物
質、例えばシリコン、ゲルマニクム、ガリウムリンの如
きものであり、その電離係数値も物質固有の値である。
Conventionally, devices using avalanche multiplication caused by impact ionization include an invat diode, an avalanche photo diode, and the like. It is known that the response speed, noise, sensitivity, and other operating characteristics of these devices depend on the ionization coefficient ratio (1/II K) of electrons and holes produced by avalanche multiplication. The substances currently known to cause sudden ionization are extremely limited to semiconductor substances such as silicon, germanicum, and gallium phosphide, and the ionization coefficient value thereof is also a value unique to the substance.

前記なだれ増倍を用いた素子の動作を最適化するには、
電離係数比を所望の値に設定することが必要であるが、
上述した如く衝突電離を起こす物質の数は限られており
、従つ【得られる電離係数比の値も限られているので、
最適の特性を与える物質が得られないケースがしばしば
生ずる。例えばアバランシェ・フォト−ダイオードにお
いて&人なだれ増倍時の増幅作用による雑音は、電離係
数比α〃が無限大又は零の時に最小となることが知られ
ている。然しなから近赤外部KJll&をもつシリコン
ではα〃が10以下であり、より長い波長域に感度を持
つゲルマニウムにおいては(1/11は2〜3程度であ
り、これ等の物質でアバランシェ・フォト・ダイオード
を形成すると雑音が太きくなるという欠点がある。
To optimize the operation of the device using the avalanche multiplication,
Although it is necessary to set the ionization coefficient ratio to a desired value,
As mentioned above, the number of substances that cause impact ionization is limited, and therefore the value of the ionization coefficient ratio that can be obtained is also limited.
Cases often arise where materials providing optimal properties are not available. For example, in an avalanche photodiode, it is known that the noise caused by the amplification effect during avalanche multiplication is minimized when the ionization coefficient ratio α is infinite or zero. However, in silicon, which has near-infrared KJll&, α〃 is less than 10, and in germanium, which has sensitivity in a longer wavelength range (1/11 is about 2 to 3), it is difficult to use avalanche photo with these materials. - Forming a diode has the disadvantage of increasing noise.

本発明の目的は、衝突電離係数比を有する既存の半導体
物質とは異なり、人為的に構成した物質構造で衝突電離
係数比を得る方法を提供することにある。
An object of the present invention is to provide a method for obtaining a collision ionization coefficient ratio using an artificially constructed material structure, unlike existing semiconductor materials having a collision ionization coefficient ratio.

本発明の更なる目的は、既存の半導体物質では得られな
い様な衝突電離係数比をも得ることカを可能な方法を提
供することにある。
A further object of the present invention is to provide a method that makes it possible to obtain impact ionization coefficient ratios that cannot be obtained with existing semiconductor materials.

本発明に係る方法においては、半導偉人と半導体Bの異
なる半導体を積層し、電子と正孔を層に平行に流した時
、電子と正孔が空間的に分離されそれぞれ異なる半導体
の層中な主とし【移動する様に設定することにより、異
種半導体の接合であっても衝突電離係数比が得られる様
にしたものである。即ち、χ^を半導偉人の電子親和力
、EgAを半導偉人の禁制帯幅、Zat−半導体Bの電
子親和双Egaを半導体Bf)禁制帯幅jと、、、、y
ると、ZA (ZB 、 Zx十EgA <”XB+B
g&     (1)を満足する様な半導体Aと半導体
Bとの交互層を少なくとも三層以上形成し、該層に平行
に電場をかけることにより上記目的を達成せんとするも
のである。
In the method according to the present invention, when different semiconductors, ie semiconductor great and semiconductor B, are stacked and electrons and holes are flowed in parallel to the layers, the electrons and holes are spatially separated and are placed in different semiconductor layers. By setting the main part to move, it is possible to obtain an impact ionization coefficient ratio even for junctions of different types of semiconductors. That is, χ^ is the electron affinity of the semiconductor great, EgA is the forbidden band width of the semiconductor great, Zat-electron affinity of the semiconductor B, Ega is the semiconductor Bf) the forbidden band width j, , y
Then, ZA (ZB, Zx10EgA <”XB+B
The above object is achieved by forming at least three or more alternating layers of semiconductor A and semiconductor B that satisfy g & (1), and applying an electric field in parallel to the layers.

更に、本発明に係る方法においては、半導偉人にアクセ
プター不純物を、半導体Bにドナー不純物を導入すると
とKより層に垂直な電界を発生せしめ、半導体Aの層に
正孔が、半導体Bの層に電子が流入するのを促進するも
のである。以下本発明につい【詳述する。
Furthermore, in the method according to the present invention, when an acceptor impurity is introduced into the semiconductor layer and a donor impurity is introduced into the semiconductor layer, an electric field perpendicular to the layer is generated by K, and holes are introduced into the layer of the semiconductor A, and holes are introduced into the layer of the semiconductor B. This promotes the flow of electrons into the layer. The present invention will be described in detail below.

第1図は上記(1)式を満足する様な半導偉人と半導体
Bとの交互層を形成した場合のエネルキー状態を示す図
である。このとき光照射やなだれ増倍などの理由で半導
偉人の層中に発生した伝導電子した正孔は半導体ムの層
中に落ち込む。その結果正孔及び電子が各々半導体A、
Bの層に分離される。ここで電子、正孔を層に平行に即
ち第1図においては、紙面に垂直な方向に加速し衝突電
離を起こさせる。衝突電離係数α、βが半導体A及び半
4体Bにおいて各k(α^、β^)、(α8.βB)で
表止孔の分離作用により、電子と正孔の衡突電離係数は
各鳥実効的にαB、β^となる。従って電離係数比とし
てα−^を得る。尚、a6及びβ^は後に述べるように
、印加電界IK依存するが、電子と正札が他の層に落ち
込む際に得るエネルギーが禁制帯幅Eg  に比し【大
きい場合Ki家、シー、の比は同一電界において更に強
駒される。
FIG. 1 is a diagram showing the energy state when alternate layers of semiconductors and semiconductors B satisfying the above equation (1) are formed. At this time, conduction electrons and holes generated in the semiconductor layer due to light irradiation or avalanche multiplication fall into the semiconductor layer. As a result, holes and electrons are transferred to semiconductor A, respectively.
It is separated into layer B. Here, electrons and holes are accelerated parallel to the layer, that is, in the direction perpendicular to the plane of the paper in FIG. 1, to cause impact ionization. When the collision ionization coefficients α and β are respectively k(α^, β^) and (α8.βB) in semiconductor A and semi-quaternary body B, the equilibrium collision ionization coefficients of electrons and holes are Birds are effectively αB and β^. Therefore, α-^ is obtained as the ionization coefficient ratio. As described later, a6 and β^ depend on the applied electric field IK, but if the energy obtained when electrons and regular bills fall into another layer is larger than the forbidden band width Eg, then the ratio of Ki family, sea, is further strengthened in the same electric field.

、に本81.カー、おい工、前述。半一体ムにアへプ、
−4純物ヶ、半導体BK)’カー不純物を導入すること
により形成した交互層のエネルキー状態を第2図に示す
。このように−各層に垂直な電界を与えることによつそ
、半導体AのJIiK正孔が、半導体Bの層に電子が注
入するのを促進するものである。
, Book 81. Carr, Oiko, mentioned above. Ahep in half,
FIG. 2 shows the energy state of alternating layers formed by introducing Kerr impurities. Thus, by applying a vertical electric field to each layer, the JIiK holes in semiconductor A promote the injection of electrons into the layers of semiconductor B.

本発明において内式を満足する組み合わせの半導4は、
岨−■族半導体、■族半導体、トl族半導体同志及びこ
れらの組4合わせによって多数存在する。具体的には、
InAs”と伽′8b の組菰会わせ、8iとQaPの
組み合わiなどがあげられる。纂 6図[InAs中の
電子の衝突電離係数αInAs及びGarb  中の正
孔の衡突電離係数βGa8bの電界強度Eに対する依存
性を示す。この図からαInA@、、’β軸は電界強度
によって変化することがわかるが、例えば電界強113
5(貼A0におけるαI山/’Garbを求めると56
である。即ち本発明によってInAsとGa8bとを積
層化した構造を用いて、第3図より求められる電離係数
比を与えるような物質を形成することが出来る。第4図
は8i中の正孔の衝突電離係数βSi及びQt中の電子
の衡突電離係数α(jaPの電界強度依存性を示す。こ
の関係から8iとGaPの組み合わせを用い【、本発明
の方法で電界強度500 (KV/c■)にお”いて、
衝突電離係数比a〃が0.02の物質を得る゛ものであ
る。
In the present invention, the combination of semiconductors 4 that satisfies the inner formula is
There are a large number of semiconductors, including A-II group semiconductors, II group semiconductors, Tol group semiconductors, and four combinations thereof. in particular,
Examples include the combination of InAs'' and Ga'8b, and the combination i of 8i and QaP. It shows the dependence on the intensity E. From this figure, it can be seen that the αInA@,,'β axes change depending on the electric field strength. For example, when the electric field strength 113
5 (Calculating αI mountain/'Garb at paste A0 is 56
It is. That is, according to the present invention, by using a structure in which InAs and Ga8b are laminated, it is possible to form a material that provides the ionization coefficient ratio determined from FIG. Figure 4 shows the electric field strength dependence of the impact ionization coefficient βSi of holes in 8i and the equilibrium impact ionization coefficient α (jaP) of electrons in Qt.From this relationship, using the combination of 8i and GaP, method, at an electric field strength of 500 (KV/c),
A substance with an impact ionization coefficient ratio a of 0.02 is obtained.

j″第5図は例とし”CInAs、Ga8bを用い【本
発明によってアバランシェ・フォト・ダイオード等を作
成する方法な説明するもので、1中1゛はGa8b或い
はGaAs基板、2はIaAsとGa8bを積層した成
長漸、3はnIJ域、4はp領域な′示す。層状構造の
作成Kit、、[1N成長法(−IJ’g )、%相成
長法(CVI) )、分子線成長法(■侶)等、通常の
エピタキシャル成長法はすべて用いることが出来る。分
子線成長法を例にとると、Ga8b或いはGaAs基板
を真空中(1×101Orr以下)で加熱(500〜6
00℃)し、In、(ja、As、8bを各々分子線と
して基板上に供給することによりInAs+ Ga8b
の単結晶薄膜を交互に層状に成長させる。n領域6.p
領域4について鳴選択的拡散法或いはIon−Impl
antat過回法により、一部分のみKn形成いはp形
不純物を導入し、層状構造の結晶にp−n接合を形成す
る。
Figure 5 is an example of a method for producing an avalanche photodiode, etc. according to the present invention using CInAs and Ga8b. In the layered growth diagram, 3 indicates the nIJ region and 4 indicates the p region. All normal epitaxial growth methods such as the layered structure creation kit, [1N growth method (-IJ'g), % phase growth method (CVI)), and molecular beam growth method (2) can be used. Taking the molecular beam growth method as an example, a Ga8b or GaAs substrate is heated (500 to 6
00°C) and supplying In, (ja, As, and 8b as molecular beams onto the substrate), InAs+Ga8b
single-crystal thin films are grown in alternating layers. n area 6. p
For region 4, the sound selective diffusion method or Ion-Impl
By the antat overpass method, Kn is formed or p-type impurities are introduced only in a portion, and a p-n junction is formed in the layered crystal.

丈に8g6図(a) (b)に本発明の方法により作成
した成長層に電極を形成する方法を示す。第6図神)(
b)で11.21は基板、12.22は成長層、5゜1
5は電極である。電極は@6図(a)のように成長層六
面或いは第6図(b)のように成長層をメサエッチング
し、そのメサ構造壁面に形成される。
Figures (a) and (b) show a method for forming electrodes on the growth layer created by the method of the present invention. Figure 6 God) (
In b), 11.21 is the substrate, 12.22 is the growth layer, 5°1
5 is an electrode. Electrodes are formed on the walls of the mesa structure by mesa-etching the grown layer as shown in FIG. 6(a) or by mesa-etching the grown layer as shown in FIG. 6(b).

このように本琵、明の方法は、アノ(ランシエーフオト
・ダイオード等の衝央電離によるなだれ増倍を用いた素
子に利用することが出来、これにより従来素子と応答速
度、雑音、感度尋の動作特性の異なる成子が得られる。
In this way, Honbi and Akira's method can be used for devices that use avalanche multiplication by impact ionization, such as Rancieffot diodes, and this results in performance improvements in response speed, noise, and sensitivity compared to conventional devices. Seiko with different characteristics can be obtained.

InAsとGarbを用いて、本発明の方法でアバラン
シェ・フォト・ダイオードを製作した場合、増倍雑音指
数が低減することによって、素子雑音が減り、最小検出
可能パワーが小さくなり、また雑音を同じ大きさとすれ
ば大きな増倍率をとれるようになる。更には入力信号−
出力信号の歪が小さくなり面周波特性が改善される等の
利点がある。即ち本発明はなだれ増倍を用いた素子の特
性を改善するものである。
When an avalanche photodiode is fabricated by the method of the present invention using InAs and Garb, the multiplication noise figure is reduced, so the element noise is reduced, the minimum detectable power is reduced, and the noise is reduced to the same level. If you do this, you will be able to obtain a large multiplication factor. Furthermore, the input signal
There are advantages such as reduced distortion of the output signal and improved surface frequency characteristics. That is, the present invention improves the characteristics of an element using avalanche multiplication.

以上訛明したように、本発明をま従来のなだれ増倍を用
いた素子において、 1)雑廿の低減化 2)高絢波特性の改善と高帯域化 6)検出可能最小入力信号をより小さくすることが出来
る 4)高効率化 等の効果を有するものである。
As explained above, the present invention can achieve the following effects in a device using conventional avalanche multiplication: 1) reduction of noise, 2) improvement of high-frequency wave characteristics and widening the band, and 6) improvement of the minimum detectable input signal. 4) It has effects such as higher efficiency.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第21は各々本発明による半導体積1−中のエ
ネルキー状態を示す図、第6図、第4図は各々本発明に
よって得られる電離係数と電界強度の関係な示す図、第
5図は本発明の層状構造の作成方法を説明する図、gg
6図(ml (b)は本発明の方法によって得られた成
長層に電極を形成する方法を示す図。 1、11.21−・・基板 2,12,22・・・成長
層5尋・・n領域 4−・り領域 5.15・・・1惨 出願人 キャノン株式会社 榊 裕之 VE (x to’ cm/v ) 、1′ お4図 争’E”   (xto−’  c竹?Vす〜   N rん)rノー)
1 and 21 are diagrams each showing the energy key state in the semiconductor product 1 according to the present invention, FIGS. 6 and 4 are diagrams respectively showing the relationship between the ionization coefficient and electric field strength obtained according to the present invention, and FIG. The figure is a diagram explaining the method for creating a layered structure of the present invention, gg
Figure 6 (ml) (b) is a diagram showing a method of forming an electrode on a growth layer obtained by the method of the present invention. 1, 11.21-... Substrate 2, 12, 22... Growth layer 5 fathoms.・n area 4-・ri area 5.15...1 Applicant Hiroyuki Sakaki, Canon Co., Ltd. Su~ N r) r no)

Claims (1)

【特許請求の範囲】[Claims] (1)χ^を半導偉人の電子親和力、Bg^を同じく禁
制帯幅、χSを半導体Bの電子親和力、l!1を同じく
禁制帯幅とすると、 KA < ze 、  KA +gg^< z11+B
gBなる条件を満足する半導体ムと半導体Bを少なくと
も三層以上積層し、該層に平行に電場をかけるととによ
り衡突電離係数比を得る方法。
(1) χ^ is the electron affinity of the semiconductor great, Bg^ is also the forbidden band width, χS is the electron affinity of the semiconductor B, l! If 1 is also the forbidden band width, then KA < ze, KA +gg^< z11+B
A method for obtaining an equilibrium ionization coefficient ratio by laminating at least three layers of semiconductor elements and semiconductor B that satisfy the condition gB, and applying an electric field in parallel to the layers.
JP56179438A 1981-11-09 1981-11-09 Obtaining method for collision ionization coefficient ratio by junction of different semiconductor Granted JPS5880879A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP56179438A JPS5880879A (en) 1981-11-09 1981-11-09 Obtaining method for collision ionization coefficient ratio by junction of different semiconductor
US06/437,627 US4553317A (en) 1981-11-09 1982-10-29 Method of obtaining an impact ionization coefficient rate by junction of different kinds of semiconductors
DE19823241176 DE3241176A1 (en) 1981-11-09 1982-11-08 METHOD FOR ACHIEVING A STOSSIONIZATION COEFFICIENT RELATIONSHIP BY CONNECTING VARIOUS SEMICONDUCTORS

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56179438A JPS5880879A (en) 1981-11-09 1981-11-09 Obtaining method for collision ionization coefficient ratio by junction of different semiconductor

Publications (2)

Publication Number Publication Date
JPS5880879A true JPS5880879A (en) 1983-05-16
JPH0526356B2 JPH0526356B2 (en) 1993-04-15

Family

ID=16065861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56179438A Granted JPS5880879A (en) 1981-11-09 1981-11-09 Obtaining method for collision ionization coefficient ratio by junction of different semiconductor

Country Status (1)

Country Link
JP (1) JPS5880879A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016190346A1 (en) * 2015-05-28 2016-12-01 日本電信電話株式会社 Light-receiving element and optical integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016190346A1 (en) * 2015-05-28 2016-12-01 日本電信電話株式会社 Light-receiving element and optical integrated circuit
US10199525B2 (en) 2015-05-28 2019-02-05 Nippon Telegraph And Telephone Corporation Light-receiving element and optical integrated circuit

Also Published As

Publication number Publication date
JPH0526356B2 (en) 1993-04-15

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