JPS588037B2 - Kōtsuushingouseigiyosouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a traffic signal control device, and more particularly to a traffic signal control device that allows a specific vehicle, such as a bus, to pass preferentially over other types of vehicles.

Conventional bus priority control systems extend green times and shorten red times to give priority to buses when they arrive before an intersection, and control only targets a single intersection. .

However, on urban streets where bus priority control is actually required, it is necessary to systematically control a group of traffic communication points on multiple routes, as seen in traffic control center systems, and between each traffic signal. Bus priority control must be performed under constraints such as synchronization and offset.

This invention was made in consideration of the above problems, and its purpose is to provide a traffic signal control device that performs priority control for specific vehicles such as buses at each intersection, and that does not disrupt system control. It is to be.

Systematic control is possible by making one cycle of traffic signal control of the traffic signals at each intersection the same, so in this invention, a specific step of the traffic signal is controlled to give priority to buses at each intersection. When the time is extended or shortened, the time of other steps is shortened or extended by the above-mentioned extended or shortened time, so that one cycle of traffic signal control at each intersection is always kept constant and equal in length. Make it.

In order to achieve the above object, the present invention includes a priority vehicle detection device that is installed in front of an intersection, detects a priority vehicle such as a bus and generates a signal, and sets a display time at each step of one cycle of a traffic signal light. a setting device for extending or shortening the display time of a specific step in response to the output signal of the priority vehicle detection device; and a store device for storing the time value extended or shortened by the changing device. and a device for shortening or extending the display time of another step by the lengthened or shortened time value stored in the store device.

With the above configuration, if a priority vehicle is detected by the detection device within a predetermined time during a step when the traffic signal light of the road is green, the change device changes the green time based on the detection and signal. This extended time value is stored in the storage device, and the display time of other appropriate steps is shortened by the stored time value to keep the length of one cycle of the traffic signal light constant. .

In addition, if a priority vehicle is detected by the detection device during a step when the traffic light on the road is red, the red time is shortened by the change device.1 This shortened time value is stored in the store device, and The display time of other appropriate steps is extended by the stored time value to keep the length of one cycle of the traffic light constant.

In this way, the traffic signal lights at each intersection perform priority control for priority vehicles, and by keeping the cycle of each traffic signal light constant, system control can be prevented from being disrupted.

Embodiments illustrating the present invention will be described in detail below.

Figure 1 is a graph showing an example of the arrangement of traffic signal lights near intersections, where ■ and ■ are respectively intersection A
Roads that intersect at 1, 2. 3 are vehicle traffic signal lights, IP and 2P are pedestrian traffic signal lights, D1 and D2 are bus detectors, and B and B2 are bus travel routes.

In FIG. 1, it is assumed that the vehicle is given priority to buses, and priority is given to passing buses only on travel route B.

Detectors D1 and D2 are installed at different distances from intersection A on road ■.

FIG. 2 is a graph showing the display steps of the traffic signal lights at intersection A in FIG.
About blue steps are indicated by a single line, red steps are indicated by ■
, the yellow step is shown as Eyo, and the blinking step is shown as 11111.

However, steps 5 and 6 are 5■, 5L, 5I and 5 respectively.
It is divided into L.

Note that the extension and shortening steps will be described later.

FIG. 3 is a block diagram showing the configuration of one embodiment of the present invention. In Figure 3, 11 is an electronic computer;
2 to 19 are registers into which the set time of each step is input from the electronic computer 11, register 12 is input with the set time of step 9, and registers 13 to 19 are input with the set time of step 1, 1, 1, respectively.
Each setting time of 2, 1, 5I, 5L, 6I, and 6L is input.

The figure shows these steps as 9, 11, 12,
1, 5-I, 5L, 6I, 6L are added to each register.

The set times of steps 9, 1 1, 1 2, 1, 5L, and 6L are extended or shortened as described later.

Other steps 2, 3, 4, 7, 8, 1
The set times of 0, 13, and 14 are fixed, and registers for setting these set times are also provided, but their illustrations are omitted.

20 is a time counter, 21 is a second pulse generator, and the counter 20 receives the second pulse from the generator 21 and measures time.

22 is a comparator circuit that compares the time value of counter 20 and register 1.
Each set value from 2 to 19 is input and compared.

23 is an OR circuit which receives the output signal of the comparison circuit 22 and the output of an OR circuit 33, which will be described later.

24 is a step counter, and the output 34 of the OR circuit 23 is a flip-flop, which is set by the rise of the output S5I of the counter 24 and by the rise of the output S7.

35 is an AND gate to which the set output of the flip-flop 34 and the second pulse from the generator 21 are input.

36 is a counter which receives the output of the AND circuit 35 and counts it.

37 is a gate, which is opened when the output S7 of the counter 24 rises, and when the gate 37 is opened, the counter 3 is opened.
A count value of 6 is input into the electronic computer 1.

38 is an OR circuit that receives the outputs of the detectors 28 and 29; 39 is an OR circuit that receives the outputs S7 to S11 of the counter 24; 40 is an AND circuit that receives the outputs of the OR circuits 38 and 39; It is said that

41 is a gate that is opened by the output of the AND circuit 40;

Reference numeral 62 denotes a register in which a fixed time value is set, and when the gate 41 opens, the set value of the register 62 is input to the computer 11.

Reference numerals 42 to 49 denote gates, which, when opened, receive the set time from the electronic computer 11 in the corresponding register 12 and step forward, and output outputs S1 to 814 that sequentially instruct steps 1 to 14. 25 and 26 are counters that time the periods of steps 5L and 6L, respectively, 27 and 28 are bus detectors corresponding to D1 and D2 in FIG. 1, respectively, 29 and 30 are AND gates, and AND gate 29 is a step counter. 24 output S
5L and the second pulse from the generator 21 are input, and the AND gate 30 receives the output S6L of the step counter 24 and the second pulse from the generator 21, and the outputs of the AND gates 29 and 30 are respectively input to the counter 25. , 26 and are counted.

The detection outputs of the detectors 27 and 28 are sent to the counters 25 and 28, respectively.
26 clear input.

31 is an AND gate, which receives the output S5L of the counter 24 and the count-out output of the counter 25 as input.

32 is an AND gate which receives the output S6L of the counter 24 and the cant-out output of the counter 26 as input.

As for the outputs of the AND gates 31 and 32, the output of the OR circuit 33 is input to the OR circuit 330, and the output of the OR circuit 33 is input to the OR circuit 23.

to 19 are input.

Reference numerals 50 to 57 are gates, and when each gate is opened, the set times of the corresponding registers 12 to 19 are input to the comparator circuit 22.

Next, the operation will be explained.

The electronic computer 11 receives the outputs S1 to S14 of the step counter 24, and outputs the respective outputs S1 to S14.
At the rising edge of , the corresponding gates 42 to 49 are opened and the time of each step is input.

From Steps 1 to 4, the display of the traffic light on road ■ in Figure 1 is normal blue, and in Steps 5 and 6, the green time of the traffic light on road ■ is classified into initial green time and extended green time. be done.

The respective initial green times, ie, times 5■ and 6■, are constant, for example, 10 seconds.

At the beginning of step 5, output S5 from counter 24
When I is issued, the electronic computer 11 selects gates 46 and 5.
4 is opened, and the time of step 5 is entered into the register 16, and the time value set in this register 16 is used as one input of the comparator circuit 22.

On the other hand, the counter 20 is reset each time the counter 24 increments, and starts counting anew with a second pulse from the generator 21.

When the time value of the counter 20 reaches the time value set in the register 16, that is, the time value of 5■, a match signal is output from the comparison circuit 22, this signal is applied to the counter 24 via the OR circuit 23, and the counter 24 steps forward and outputs S
Produces 5L.

At this time, the counter 20 is reset and starts counting anew.

As the output S5L of the counter 24 is generated, the gate 4
7 and 55 are opened, the set time of step 5L is input to the register 17, and the time value set in this register 17 is applied to the comparator circuit 22.

The time of step 5L set in the register 17 is the maximum value of the extension time in step 5.

Therefore, if the maximum extended green time elapses while the gate 54 is open, a match signal is output from the comparator circuit 22 and the counter 24 increments.

On the other hand, the output S5L is applied to the AND gate 29 to open it, and the second pulse from the generator 21 is applied to the counter 25 via the AND gate 29, and the counter 25 starts timing.

The counter 25 indicates the unit extension blue time (
This is considerably shorter than the maximum extended blue time set in register 17.

), and generates an output signal when the unit extended green time is completed.

However, when the detector 27 detects a bus, the counter 25 is cleared by its detection output, so if there is a bus at the position of the detector 27, no signal is generated from the counter 25.

In this case, when the bus passes the position of the detector 27, the counter 25 starts counting anew.

When a signal emerges from the counter 25, this signal is applied to the AND gate 31, which then outputs S5.
Since the counter 25 is opened by L, the signal of the counter 25 is passed through the AND gate 31 and the OR circuits 33 and
4 and advance it.

Counter 24 increments and produces output S6I, which closes gates 47 and 55 and opens gates 48 and 56.

That is, during the period of step 5L, when the bus detection output from the detector 27 does not exist or ceases to exist, the clock value of the counter 25 reaches the unit extended green time, and an output signal of the counter 25 is generated, and the output signal of the counter 25 is generated. is incremented and proceeds to step 6, but the counter 25
If the output signal is not output until the maximum extended blue time set in the register 17 has elapsed, a match signal is generated from the comparator circuit 22 when the clock value of the counter 20 reaches the maximum extended blue time value, and the counter outputs the matching signal. 24 and proceed to step 6.

Note that after the counter 25 starts timing within the period of step 5L, it is cleared when the detector 27 detects the bus and produces an output, and starts counting again when the detection output of the detector 27 disappears. , the above operation is repeated every time a detection output is output from the detector 27.

At step 6, the counter 24 first outputs S5I.
is issued, the gates 48 and 56 are opened, and the set time of step 6I is sent from the computer 11 to the register 18 (this is the initial green time in step 6).

) is input, and the initial green time value set in the register 18 is input to the comparison circuit 22.

The counter 20 is reset at the rising edge of the output S6I of the counter 24 and starts counting anew, and when the measured value becomes equal to the time value set in the register 18, the comparator circuit 20
A match signal is output from 2 and applied to the counter 24 via the OR circuit 23, causing the counter 24 to increment.

The counter 24 therefore produces an output S6L, at which time the gate 49.57 opens and the maximum extended green time value in step 6 is input into the register 19, and this time value set in the register 19 is input into the comparator circuit 22. .

The counter 20 is reset by the output S6L and starts counting anew.

Output S6L is further applied to AND gates 30 and 32.

Therefore, the AND gate 32 is opened and the counter 26 receives the second pulse from the generator 21 and starts timing.

The counter 26 produces an output when it finishes counting the unit extended green time in step 6L, and this output is applied to the counter 24 via the AND gate 32 and the OR circuits 33 and 23 to increment it. However, if the detector 28 produces a sensing output in the meantime, this sensing output is added to and clears the counter 26.

The counter 26 is cleared by the output of the detector 28,
Further, the operation of the counter 26 restarting time counting when the output of the detector 28 disappears is exactly the same as that described for the counter 25.

With this operation, if the time value of the counter 26 reaches the unit extended green time value before the maximum extended green time set in the register 19 has elapsed, the counter 24 is incremented by the output of the counter 26, and the step is stopped. Proceed to step 7.

However, if no output is generated from the counter 26 until the maximum extended blue time set in the register 19 has elapsed,
When the maximum extended green time has elapsed, the time value of the counter 20 reaches the maximum extended green time, a match signal is generated from the comparison circuit 22, the counter 24 is incremented, and the process proceeds to step 7.

On the other hand, at the beginning of step 5, the output S from the counter 24
When 5I occurs, flip-flop 34 is activated at the rising edge.
is set, AND gate 35 opens, the second pulse from generator 21 is added to counter 36, and counter 36
starts timing.

Next, the process advances to step 7, and when the output S7 is output from the counter 24, the flip-flop 3 is activated at the rising edge of the output S7.
6 is reset and the AND gate 35 is closed.

Therefore, at this point, the time counting by the counter 34 ends.

That is, the time value of the counter 34 is the period of steps 5 and 6, and this period differs depending on the time when the outputs of the counters 25 and 26 are generated, respectively.

Note that the output S. of the counter 24 is 7, the gate 37 is opened and the time value of the counter 36 is input to the electronic computer 11.

By the way, in steps 5 and 6, the detectors 27 and 28
If neither detects a bus, then step 5,
The actual time of 6 is the sum of the periods of the outputs S5I and S6■ of the counter 24 and the unit extended blue time of each of S5L and S6L.

However, if the counters 25 and 26 are cleared due to the detection of the bus during the period S5L and white 6L, the actual time of steps 5 and 6 will be extended by that much.

In steps 5 and 6, it is assumed that no bus is detected.As shown in Figure 4, step 5 is a combination of the initial blue time set in the register 16 and the unit extended blue time set in the counter 25. Step 6 is the sum of the initial blue time set in the register 18 and the unit extended blue time set in the counter 26.

Furthermore, in steps 5 and 6, if the buses are detected one after another and neither the counters 25 or 26 generate a timing completion signal, the time in step 5 is determined by the initial blue time set in the register 16, as shown in FIG. time and register 17
is the sum of the maximum extended green time set in step 6.
The time is the sum of the initial blue time set in register 18 and the maximum extended blue time set in register 19.

However, for the sake of convenience in Figure 4, 5I and 5I are the initial green time,
5L and 6L indicate the maximum extended green time, and 25.26 indicates the unit extended green time, respectively.

In addition, in steps 5 and 6, after the counters 25 and 26 are cleared once each by bus detection, time measurement is restarted and a time measurement completion signal is generated.The length of steps 5 and 6 is shown in Figure 4 C. It's time to show.

However, points a and b in C indicate the points at which the counters 25 and 26 restart timekeeping, respectively.

Compare A and C in Figure 4 with the mouth, and step 5.
You can see the extended time of 6.

The electronic computer 11 transfers the time value of the counter 36 to the counter 24.
The time value inputted at the output S7 of , and extended during the period of steps 5 and 6 is calculated, and this calculation period is allocated to the subsequent steps 911 and 12 to shorten the time of these steps.

For example, if the extended time is 12 seconds as a result of the calculation, this will be allocated to steps 9, 11, and 12 in a ratio of 5:5:2, and the times for steps p and 11 will be shortened by 5 seconds. , the time of step 12 is reduced by 1 second.

In this case, the electronic computer 11 outputs S9 from the counter 24.
is issued and gate 42.50 opens, register 1
2, input the value shortened by 5 seconds as the setting time of step 9, and when the output S11 is output from the counter 24 and the gates 43 and 51 are opened, the value of step 1 is input to the register 13.
A value shortened by 5 seconds is input as the setting time of 1, and an output S12 is output from the counter 24 and the gates 44 and 5
When 2 is opened, a value shortened by 2 seconds is input into the register 14 as the setting time of step 12.

In this way, when the green time of road (2) is extended due to the detection of a bus in steps 5 and 6, the green time of road (2) is shortened by the extended time in steps 9 and 11.12.

Steps 9, 11 and 12 are as shown in Figure 2.
is the blue period, and furthermore, in step 9, the signal lamp 2P is also blue.

This means that when the green time on road ■ is extended to give priority to buses, the green time on road H is shortened by the extended time.

In this manner, the bus priority control is performed, and the length of one cycle of the traffic signal is maintained at a constant time.

In the embodiment shown in FIG. 3, 5L of step 5
When the bus priority road ■ detector D1 detects a bus during the period , the time of 5L is extended so that the bus can pass through the intersection A without stopping. During the 6L period, if the detector D2 detects a bus due to a reason such as the presence of a following bus, the 6L period is extended so that the following bus can also pass through the intersection A without stopping. .

The above also applies if the bus detected by detector D, has not passed the position of detector D2 during the extended period, even though step 5L is extended due to slow running speed etc. Step 6L was extended again as shown in the following.

Next, in steps 7, 8, 9, 10, 1 1, where the traffic signal light 1 of road ■ is yellow or red,
When the bus is detected by the detector 27 or 28, their detection outputs are input to the AND circuit 40 via the OR circuit 38.

At this time, one of the outputs 97 to S11 of the counter 24 is applied to the OR circuit 39, and since that output is present, the output of the AND circuit 40 is present, and this output opens the gate 41, setting the register 62. The value is entered into electronic computer 11.

Based on this input, the electronic computer 11 performs step 9,'
11. The time of 12 is shortened by the time set in the register 62.

However, for example, when a bus is detected in steps 7 and 8 and the set value of the register 62 is input to the computer 11, the computer 11 transfers the set value in step 9,
11 and 12 to shorten each step. For example, when a bus is detected in step 11 and the set value of the register 62 is input to the computer 11, the computer 11 steps by the set value of the register 62. Reduce the time of 12.

When such a shortening is performed, the electronic computer 11 memorizes this, and when the output S1 of the counter 24 is output and the gate 45.53 is opened, the electronic computer 11 sets the step 1 in the register 15. As the time, input a time value extended by the shortened time value.

When the time is reduced in steps 9, 11, and 12 in this way, the time in step 1 is extended accordingly.

In other words, when a bus approaches an intersection on a road with bus priority while the traffic light on that road is red, the green time of the other road with a green light will be shortened, and the red time of the bus priority road will be shortened accordingly. In this way, in addition to shortening the waiting time for buses, the green light time on roads where buses have priority is extended to keep the length of one cycle of the traffic signal light display constant, so as not to disrupt system control.

As explained above, the present invention includes a priority vehicle detection device (detectors D1 and D2 in the embodiment) and a setting device (registers 12 to 19 in the embodiment) for setting the display time at each step of one cycle of a traffic signal light. ) and a changing device (in the embodiment, a counter 25
, 26 and AND circuit 40). A store device (
In the embodiment, it comprises a counter 36 and a register 62) and a device for shortening or extending the display time of other steps by the changed time value stored in the storage device,
Since the length of one cycle of traffic signal lights is kept constant, it is possible to give priority control to specific vehicles such as buses at each intersection without disrupting system control.

[Brief explanation of the drawing]

FIG. 1 is a graph showing an example of the arrangement of vehicle detectors in this invention, FIG. 2 is a graph showing steps for displaying traffic signal lights, and FIG. 3 is a graph showing the configuration of one embodiment of this invention. The graph shown in FIG. 4 is an explanatory diagram of the operation. D1, D2... bus detector, 11... electronic computer,
12 to 19...Register, 20...Time counter, 24...Step counter, 25.26...Unit extension blue time counter, 28, 29...Bus detector, 36...Time counter , 40...AND circuit,
62...Register.

Claims (1)

[Claims] 1. A priority vehicle detection device installed in front of an intersection that detects a priority vehicle and generates a signal, and a setting device installed to display the display time at each step of one cycle of a traffic signal. a storage device for storing the time value extended or shortened by the modification device; and only the extended or shortened time value stored in the storage device. A traffic signal control device comprising a device for shortening or extending the display time of other steps, and adjusting the length of one cycle of a traffic signal light to be kept constant.