JPS587882A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable high speed operation by isolating a drain or a source from a substrate via an insulator, thereby reducing a floating capacity. CONSTITUTION:Part of a single crystal layer 32 including an impurity to become a gate is formed in contact with a substrate single crystal on a silicon substrate 30. A single crystal layer 33 including an imputrity to become at least either one of a drain or a source is formed through an amorphous insulator 31 on the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly an integrated circuit using a silicon substrate, and more particularly to a junction field effect transistor and an integrated circuit device including the same.

Integrated circuits using silicon substrates are bipolar, which uses so-called planar technology, and hK), which uses silicon surfaces.8
(Metal 8i1icon-dioxide f
iemiconductor) type integrated circuits, especially M
The Oa type is used in an extremely large number of integrated circuits due to its high degree of integration and unique features, and has reached the point where it can be provided with surprising functions, as seen in l-chip microcombinators and the like. In this way, it is currently bipolar type or M)
8-type transistors are often used, but unlike other junction-type field effect transistors, it is difficult to separate the transistors and occupies a large area, making it difficult to achieve high integration. Further, driving at a low voltage requires a thin epitaxial layer with a steep impurity concentration profile. However, with the use of reduced pressure epitaxial equipment and ion implantation equipment, these restrictions are being gradually lifted.

FIG. 1 shows a cross section of a planar junction field effect transistor that has been widely used in the past. pm
An epitaxial WX2 of nfJ is formed on a silicon substrate 1 containing a high concentration of impurity of n-type, a source 3 and a drain 4 containing high concentration of n-type impurity are formed by diffusion, and a gate 5 is further formed with a high concentration of Kp-type impurity layer. Also, since the element separation section 6 is similarly formed and the planar structure is easy to integrate. However, since the isolation is based on the p-n 8 coupling, there are disadvantages in that the area required for isolation is large and the stray capacitance becomes large.

Diagram N2 is from the Journal of Solimado State Circuit (IlaB JOURNALO).
F 80LID-8TATE CI[TJIT8)rI
PP (ME 5C-15-8 No. 4 656-660
This is an example of a buried junction field effect transistor described in a paper by Minato Osamu and six others listed on the page. This element is a complementary element in the NW board 10.
It passes through the 2m region 11 which becomes the gate formed at the same time as the p-type diffusion layer called p-well in MOS, and further forms the drain 12 and source 13.
In the example of this paper, this junction field effect transistor is used as a load, the power source is taken from the substrate, and the gate region t! I/,]
] is a complementary CMO8 (D p-well), so the drain gate of the junction layer field effect transistor can be taken out to the substrate by taking out the entire integrated circuit, and the star only has to take out the source electrode, which increases the degree of integration. However, in this structure, the base region is fabricated at the same time as the p-well, so
The so-called bonding depth to the substrate is 4 microns, and its size is naturally limited due to lateral diffusion and expansion, and creating a pattern of about 1 to 2 microns will be a major obstacle for high-density integration. . Additionally, this junction field effect transistor is a special use case, as integrated circuits based on this type of transistor typically require an additional ohmic junction to the gate region and isolation between the transistors; The object of the present invention is to create a semiconductor with a structure that can withstand general use, which was previously difficult, and that is highly suitable for ultra-high density. The goal is to provide equipment.

According to the present invention, a monocrystalline layer containing impurities is formed on a silicon substrate, a part of the single base layer that becomes the gate part is in contact with the single crystal substrate, and the monocrystalline layer contains impurities and becomes at least one of the drain part and the source part. It is possible to obtain a semiconductor device characterized in that it includes a structure in which the semiconductor device is placed on a substrate via an amorphous insulator.

#Distribution According to the present invention, since the drain and, if necessary, the source can be separated from the substrate by an insulating material, stray capacitance can be reduced and an integrated circuit capable of high-speed operation can be obtained. Furthermore, since membrane separation is always used, a hybrid of n-channel and p-channel is possible on the same substrate, and a complementary circuit configuration is possible. Further, by appropriately selecting the distance between opposing gates and the impurity distribution, it is possible to obtain both enhancement deaf and depletion expansion type transistors.

Furthermore, since the silicon layer on the insulating film is single crystal, it is possible to integrate various active or passive elements on the same substrate on this single crystal film.

FIG. 3 shows the steps and structure of manufacturing a junction field effect transistor according to the first embodiment of the present invention. First, an insulating film 31 such as a silicon oxide film or a nitride film is formed on the surface of a silicon substrate by thermal oxidation or the like.

This is then subjected to a photolithography process to open a portion where a gate will be formed and expose the silicon substrate. Next, silicon is epitaxially grown using hydrogen-diluted 8x C1 and hydrochloric acid mixed gas at a substrate temperature of about 1080°C and a reduced pressure of f3QTorr. At this time, boron (Ro) is added in the first step to give p-type conductivity. ), and in the second step, doping with phosphorus [F] or arsenic (As) to give conductivity of 32.
When 33 epitaxial silicon layers are obtained, Figure 3 (1
). Subsequently, a 40 to 100 nm 9 degree silicon oxide film 34 and a silicon nitride film of about 100 to 200 nm are deposited by vapor phase growth, leaving a portion where the transistor will be mounted by photolithography, and then this silicon is deposited. Using the nitride film as a mask, the unmasked portions are diffused with boron (B), which becomes Kp type, and then thermally oxidized, resulting in a structure as shown in FIG. 3(b). In this way, the leakage current at the side surface of the channel can be suppressed. Next, a nitride film 39 and an underlying oxide film are left by photolithography at the location where the gate region on the front side is to be formed.N-type impurities are then diffused and then covered with a relatively thick oxide film C by thermal oxidation. A total of 41 source and drain regions can be obtained. Through these steps, the base region 32, which is initially formed by filling, has a shape that is slightly expanded upward and downward, as shown at 43. Finally, the t-oxide film is removed and a gate region 4 on the surface side is formed by a relatively leaky impurity introduction method such as ion implantation to obtain a lateral junction field effect transistor as shown in FIG. 3(e). It goes without saying that in addition to the impurity doping methods used in these processes, various methods such as thermal diffusion and ion implantation can be used by appropriately selecting the thickness of the mask material. .

In the first embodiment of the present invention, since the source and drain are electrically isolated from the substrate and surrounding elements by the insulating film, extremely high speed operation is possible. Since the source and drain are separated from the substrate, the grown epitaxial layer may be removed by photolithography. Furthermore, if there is a sufficient distance between the elements to be separated, the above-mentioned epitaxial method using 8sH2CI□ can be used to form an amorphous film such as a silicon oxide film or a nitride film under the opening of the insulator. It is possible to grow the single crystal silicon as a seed and to spread the silicon single crystal laterally from the opening surface so that the silicon single crystal grows only around the opening.

Therefore, since the junction field effect transistor formed in the O opening and the surrounding elements can be naturally separated, it is possible to form an integrated circuit on the same substrate without using the above two methods. can.

FIG. 4 shows a twenty embodiment of the present invention, in which the source or drain group and the gate 51 are electrically isolated by a p-fl junction and separated from the substrate by a special isolation I/# film. There isn't. However, the drain or source 52
is oxidation I! Since it is separated from the substrate by 453, load capacitance can be eliminated in many cases, similar to the IIgl embodiment, and high-speed operation is possible.

The second embodiment is shown in FIG. 3 (
Since the insulator opening in 1) is formed up to the region where the source or drain portion is to be formed later, the gate buried layer can be formed in the same process as the first embodiment.

In the above embodiments, an n-channel plastic element has been described, but even those who are not semiconductor-related engineers can easily infer that a p-channel structure can be manufactured, and it is actually easy to manufacture the element.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing a cross section of a conventionally used junction-separated lateral junction field effect transistor. 1 is a substrate, 2 is an epitaxial layer, 3 is a source, 4 is a drain, 5 is a gate, and 6 is a diffusion layer for element isolation. Figure 2 shows an example of elements used in integrated circuits that are useful for increasing density. 11 is the substrate, 12 is the source, 1
3 indicates the drain, and 14 indicates the gate. FIG. 3 is a diagram for explaining the first embodiment of the present invention and its manufacturing process, in which numeral 31 is a substrate, 31 is an insulator, 32. &3 are epitaxial layers that become gate and channel parts, respectively;
U is a silicon oxide film, weak is a silicon nitride film, A is a diffusion layer for leak prevention, 37 is an insulating film for isolation between elements, 38
．． 39 is silicon oxide film and nitride film, season is source, 41
is a drain, 4 is a silicon oxide film, 43 is a buried gate layer, and 4441dMM gate layer. FIG. 4 shows an example of @2 of the present invention, where 51 is a source or drain, 51 is a buried gate layer, 52 is a drain or source, and 52 is an insulating film electrically insulating it from the substrate. .

Claims (1)

[Claims] A part of the single crystal layer containing impurities formed on a silicon substrate, which will become the gate part, is in contact with the single crystal substrate, and the single crystal layer containing impurities, which will become at least either the drain part or the source part, is amorphous. 1. A semiconductor device comprising a structure installed on a substrate via a high-quality insulator.