JPS587877A - Insulated gate static induction transistor - Google Patents

Abstract

PURPOSE:To improve the integrating density of a transistor by displacing the position of the second n<+> type main electrode region in a P type region and providing a distribution in the impurity density in the P type region, thereby reducing reactive current. CONSTITUTION:A conductive type first main electrode region 11 and a reverse conductive type region 13 are formed in space in a conductive type low impurity density semiconductor region 10. A conductive type second main electrode region 12 is formed in the region 13, and an insulating gate electrode 3 is formed on the region 13 between the first and the second main electrode regions. The distance W1 between the second junction 22 between the second region 12 and the region 13, and the first junction 21 between a low impurity density region 10 and the region 13 is formed in the shortest length. For example, the surface impurity densith at the region 13 side of the second junction 22 is, for example, preferably reduced to the lowest at the side W1 confronting the first main electrode region.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate lid static induction transistor (MIS/SIT) with improved characteristics.

Mlg-111? In particular, as disclosed in Semiconductor Research Vol. 15, pp. 168-171 (Industrial Research Fund, 1978), Mo1t-11T has superior high-speed performance compared to the conventional MOB 1mt, and can be used as a logic circuit. Sometimes they are characterized by low power consumption. There are various structures of MOB ext, and No. 111 (@) shows a cross-sectional view of one of the conventional examples. For example, No. 11 main electrode regions 11 formed at intervals on a Psf area 15 and yl
Consisting of a second main electrode region 12 inside a region 13,
M engineering S consisting of an insulating film (mainly an oxide film) 4 and a gate electrode 3
(or MOS) gate electrode is placed on the surface of the P-type head region 13 at the first. It is formed between the second main electrode regions 11.12. This MOS-8 engineering T is the 1st. When the second main electrodes 1 and 2 are respectively used as drain and source, a potential barrier controlled by the gate voltage and the drain voltage is generated in the front surface of the source mainly under the gate electrode 5 in the P-type head region 13, and carrier injection from the source is caused. It has the characteristic of exhibiting unsaturated characteristics in which the drain current flows through a conduction mechanism that controls the amount, and is mainly used in enhancement mode. At least in common parts of the main operating area, the first. Second main electrode area 11.1! Since the impurity density between the % type substrate region 10 and the P type region 15 is low enough to form a depletion layer, the junction capacitance is extremely low, and together with the unsaturated characteristics, high speed and low power consumption operation is possible. However, in this structure, since the second main electrode region is formed symmetrically to the center of the P-type region 15, electrons flow out from the second main electrode region 12 in all directions especially when the pressure is low (G). However, it has the disadvantage that the drain current (leakage current) increases in the so-called off state.

This is a MOS-8 in which the P-type head region 1S has a low impurity density.
This is a noticeable phenomenon with one gun. In addition, there are two MOs inside the IO.
S-3 engineering T Trl and Tr2 are located next to each other in Figure 1 (
In a structure example like b), the first electrode 101 of Trl and Tr
When there is a potential difference between the second of 2 and the pole 202, 'I'
A current flows from the second electrode 202 of r2 to the Trl side, and the S and T are not sufficiently separated from each other. If the distance between the two 81Ts is sufficiently widened to prevent this, the opposite effect will occur in that the integration density will decrease.

The present invention is based on the conventional MOS shown in FIGS. 1(g) and (b).
- This was made to improve the drawbacks of one structural example of BIT. The first purpose is to reduce current due to parasitic effects, reduce leakage current, and improve off-state characteristics. The second purpose is that the separation of two or more BITs is sufficient;
Moreover, the purpose is to provide a structure that improves the integration density. The present invention will be described in detail below with reference to the drawings.

FIG. 2 (6) shows a cross-sectional view of the M-work 8/BIT according to the present invention, corresponding to the conventional example shown in FIG. 1 (α). 2nd electrode 1 main electrode area 1
2 is formed biased toward the first main electrode region 11 side, and connects the first junction 21 (between the P-type head region 13 and the cross-shaped substrate 10) and the second
The distance of the junction 22 (between the second main electrode region 12 and the P-shaped head region 13) is the shortest on the first main electrode 11 side. Zero bias (gate voltage; drain voltage WO
W) When the neutral region remains in state 1. The shortest distance W between the second junctions 21.22.

is the distance W of the other part, and the relationship is -・''≧2 mu weight Wl (effective bonding area with the distance 1ilIW, the distance between the first and second bonding of W, respectively). If there is, the 1r current flowing out from the portion of the distance @V is approximately half or more of the other portions, that is, the reactive current is 50% or less, and is approximated to zero order. Assuming that the second main electrode region 12 is a cube, if we want to effectively flow out carriers from the - plane, '/A1m
/4, so W, 7. ≧~8 is desirable.

If BIT is sufficiently long in the cross-sectional direction of FIG. 2 (!α) and the bottom surface and longitudinal ends of the second main electrode region 12 are ignored, it can be approximated as W*/, ≧˜2. Furthermore, if the P-type head region 13 with a width of V, ,V is depleted and the heights of potential barriers formed there are vl and vl, the number of carriers on the potential barrier is asp(-t > t axp <-) is proportional to q
vtomi can be approximated.In order to make the reactive current less than IQ%
person, asp (-p) mu* '”F (-naka
) ≧ 10. For simplicity, A1 #A
If @, then v, -v, ≧ ~ [L06v, and if V, is the diffusion potential vAi (an almost neutral region remains in the center of W), then v1≦vbt-CLo6(v). .

For simplicity, if the impurity densities of the P-type head region 13 and the cylindrical substrate 1o are approximately equal, and the spread 7 of the depletion layer toward the cylindrical substrate 1o is W%, then y, / y, #'Y @
If #'r h L, then W, #2WW (when W, is small), so V! For example, if you substitute 1・'61 for i, WB
2. ,≦lls That is, by making v more than three times as much as t, OGf, the reactive current can be reduced to less than IQ%.Pl! What has been described above is the case where the impurity density in region 13 is almost uniform, but PWi region 1! with WB4D width and W, 0 radiation! By changing the impurity density of i, the reactive current can be further reduced. The impurity density of the portion W in the type 1 region 15 is n, and the impurity density N of the portion W is.

If it is lowered by one order of magnitude, the diffusion potential will drop by about 106V, and the reactive current will be about /. The above W becomes W.

If used in conjunction with making it narrower, the reactive current can be reduced to approximately 1-.

To achieve the above, after forming the PWi region 13 by diffusion, the formation hole is made in the second main electrode region shifted from the previous IIl diffusion hole, and a second hole is formed in the lateral diffusion region of prtii diffusion. All you have to do is make sure that there are two junctions.

It is also effective to directly lower the effective P11M impurity density in the W portion by ion-implanting % base impurities through the gauge oxide film 4.

MOi9-! according to the invention! i-engineering! The reactive current is 1 compared to the conventional
Since it can be reduced to 0 to 1 attack or less, the separation distance between S ets can be shortened. Therefore, there are two or more different B works in the same pg area 13! 0% 10th second main electrode area 112, 212
．． . . . forming second main electrode regions 112, 212. The distance between... is 018 as described above.
If the above is taken, the separation of each S-work T is sufficient. two B's
An example applied to IT Trl and Tr2 is shown in Figure 2(b).
Shown below.

The S1 unit according to the present invention is easily realized by conventional processes. 3rd @! (am) is, for example, 1×10 “m”
() shows a cross section where &a is selectively implanted into the substrate 10 to form an r-type region 1s with a surface density (for example, Iol·m= ) to a depth of 3μ by diffusion.
The 0810m film 15 on the rm region 15 can be made thinner than the 810m film 15 on the other surface. In Figure 5 (h),
旙＋diffusion hole #11. 1 row of 2nd main 1st main electrode,
In particular, in the second main electrode region, the forming hole is formed in the first main electrode region 11, showing a cross-connected and diffused (for example, depth L12) fragment.
It is necessary that the end portion of the Pml area on the opposite side overlaps with the ink forming hole and is small. The edges of the holes can be aligned by ±(15μ~±a,
It can be done with a 25μ habit. meeting, sio, membrane 5 and 111
0. By utilizing the difference in film thickness, the ends can be aligned in a self-aligning manner. In this case, since the opening for the first main electrode area 1 is made, the resist is then baked at a high temperature and made to flow to protect the opening for the second main electrode area, and then S10. It is desirable to perform etch, as shown in Figure 5 (O
), the gate oxide film 40 part, contact 4 as necessary.
Section 110. The cross section after selective etching and oxidation is shown. The thickness of GeF oxide J[4 is usually about 500 to 20,001 mm. After that, the first . The first main electrode 1.2, gate electrode 5 and necessary wiring are completed as shown in FIG. 3Cd>.

In the first Wioa sentence, W is about t5μ and F of the second junction is
The Wi surface impurity density is 2×10"a- or less. On the other hand, "l" can be selected at any value of several microns or more, and is high at 1011♂ just below the PIE surface impurity density of the second junction. If the S diffusion is made deeper, it is possible to make %"l narrower and lower the impurity density.
Although we have described the case of MO8, it is also possible to use a gate electrode made of other wiring materials such as polysilicon or MO*81s"all'e oxide film, or a gate F insulating film made of a multilayer or mixed film with an oxide film. Further, the present invention can be applied to a P-channel transistor in which the conduction type of each region is reversed, and the first main electrode 1 is used as the source electrode.
0 described an example using bulk. But, %on s, s
It can also be applied to epitaxial layers depending on the purpose, such as Hy or a combination of opposite conductivity, those with a buried layer, and those on an insulating substrate.

As described above, the present invention shifts the position of the main electrode region 120 of the cylinder 2 in the pm region 13 and further distributes the impurity density in the PIilI region, thereby realizing mXT in which the reactive current is smaller than the conventional one by more than to. , which provides an advantageous structure for integration, and is applicable to all conventional 0NOT II and Xa.

[Brief explanation of drawings]

11j←1 and Cb) are respectively conventional VOl/False! ! 2 (@) and (h) are cross-sectional structural examples of Mol-mXT according to the present invention. No.! Figure 1 (art) - (i is a cross section m* along the manufacturing process of Mo1-mXT according to the present invention. 1.101, 201...First main electrode!, 102
,202-...Second main electrode 1.10iS, 20!
I...Gate electrode 4.104,204-...
・・Gate insulation cry o-----smst substrate 11, 111, 211...... Sanju 1st main electrode area 1, 2, 112, 212... Bokaku 2nd Main electrode area or more'-10

Claims (1)

[Claims] (1) A first main electrode region of one conductivity type and an opposite conductivity layer region spaced apart from each other in a conductivity type low impurity density semiconductor region, and a -conductivity type region formed within the opposite conductivity type region. 1j
lH main electrode area, j11 and second main electric field area OU
In a transistor comprising an insulated gate electrode co-formed with a small amount *fi on the opposite conductivity region, the second main electrode region and the opposite conductivity type region owio second junction, the low impurity density region and the conductivity region An insulated gate type electrostatic induction transistor, characterized in that a distance between the first and second regions is the shortest on the side facing the first main electrode region.佽） Saikan! 2. The insulated gate static induction transistor according to claim 1, wherein the surface impurity density on the opposite conductivity type region side of the weld is lowest on the side facing the first main electrode region. (1) The insulated gate type electrostatic induction according to claim 1 or 2, wherein the second main electrode regions of the plurality of transistors are formed in the reverse conductive layer region. transistor.