JPS5877251A - Ic package - Google Patents
Ic packageInfo
- Publication number
- JPS5877251A JPS5877251A JP56176034A JP17603481A JPS5877251A JP S5877251 A JPS5877251 A JP S5877251A JP 56176034 A JP56176034 A JP 56176034A JP 17603481 A JP17603481 A JP 17603481A JP S5877251 A JPS5877251 A JP S5877251A
- Authority
- JP
- Japan
- Prior art keywords
- package
- capacitor
- lsi
- power source
- electric power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
Description
【発明の詳細な説明】
本発明はＩＣパッケージに係シ、特に集積回路チップ上
の電源端子の電圧変動を小ならしめうるＩＣパッケージ
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an IC package, and more particularly to an IC package that can reduce voltage fluctuations at power supply terminals on an integrated circuit chip.
ＩＣパッケージがその内に封入された半導体能動素子自
身の特性に与える影響については従来から色々と調べら
れている。特に近年高速の論理ＬＳＩや広帯域アンプな
どではパッケージのリード部分がインダクタンス成分を
持ち、ＬＳＩ自身の特性に悪影響をおよぼす事が知られ
ている。Conventionally, various studies have been conducted on the influence that an IC package has on the characteristics of the semiconductor active device itself sealed therein. Particularly in recent years, it has been known that in high-speed logic LSIs and broadband amplifiers, the lead portion of the package has an inductance component, which adversely affects the characteristics of the LSI itself.
従来Ｌ８Ｉへ供給する電源のレギュレーシ冒ンを良くす
る一手段としてＩＣパッケージの電源ビレと接地（以下
、ＧＮＤと呼ぶ）ビンの間に・・デンサーを挿入する方
法が一般に行われている。Conventionally, a method of inserting a capacitor between the power supply pin of the IC package and the ground (hereinafter referred to as GND) pin has been generally used as a means of improving the regulation of the power supply to the L8I.
これはＩＣパッケージのリード部の抵抗成分とインダク
タンス成分が無視出来る時には電源装置の電圧変動に対
して有効に働くばかシでなくｓ ＬＳＩ自身の動作によ
って引き起される。ＬＳＩチップの電源端子（以後ＶＤ
Ｄ端子と呼ぶ）の電圧変動に対しても有効に働く。しか
し前記ＬＳＩの動作周波数が高くなると前記ＩＣパッケ
ージのリード部分のインダクタンス成分が目立ち始め前
記ＩＣパッケージの電源ピンとＧＮＤピンの間に挿入さ
れたコンデンサーはＬＳＩ自身の動作に起因す今ＶＤＤ
端子の電圧変動に対してはその効力を失う結果となる。This is caused by the operation of the S LSI itself, not by the fact that it is effective against voltage fluctuations in the power supply when the resistance and inductance components of the leads of the IC package can be ignored. Power supply terminal of LSI chip (hereinafter referred to as VD
It also works effectively against voltage fluctuations at the D terminal. However, as the operating frequency of the LSI increases, the inductance component of the lead portion of the IC package becomes noticeable.
As a result, it loses its effectiveness against voltage fluctuations at the terminals.
本発明の目的はＬＳＩ自身の動作によって引き起される
ＶＤＤ端子の電圧変動を極小ならしめ得るＩＣパッケー
ジを提供することにある。An object of the present invention is to provide an IC package that can minimize voltage fluctuations at the VDD terminal caused by the operation of the LSI itself.
本発明はＩＣパッケージ内部の電源端子用ステッチとＧ
ＮＤ端子用ステッチの間に適当な方法で容１ｋを作シ込
む事によＪＩＩＣＩＣパッケージド部分のインダクタシ
スの効果を事実上キャンセルし１ よってＬＳＩ自体の
動作による前ｇＱＬｓｉチップの電源端子の電圧質＃を
無くし前記ＬＳＩの安定な動作をｏＪ能にするものであ
る。The present invention features stitches for power supply terminals inside an IC package and
By inserting a capacitance of 1k between the ND terminal stitches using an appropriate method, the effect of inductance in the JIICIC packaged part is effectively canceled.1 Therefore, the voltage quality of the power supply terminal of the previous gQLsi chip due to the operation of the LSI itself is reduced. # is eliminated to enable stable operation of the LSI.
次に本発明による容量の働きを説明する。第１図（ａ）
は従来の方法でコンデンサーを挿入したときの外観図、
同図（ｂ）は同図（ａ）の等価回路會表わしている。今
ＬＳＩが動作周波数ωで動作しているとする。そしてこ
のωに同期してＬＳＩチップ２の電源、ＧＮＩ）端子間
のインピーダンスが変化したとすると、そのインピーダ
ンスの変化に応じて前記Ｌ８’Ｉの電源電流がある時定
数を持って変化する。するとパッケージリード部の抵抗
１のために、前記電流変化によって電源端子に電圧の変
化が生じる。一方、前記電帆変化率を７こ とするとパ
両者によって電源端子の電圧は大きく変動する。Next, the function of the capacitance according to the present invention will be explained. Figure 1(a)
is an external view of the capacitor inserted using the conventional method.
FIG. 5(b) shows an equivalent circuit diagram of FIG. 1(a). Assume that the LSI is now operating at an operating frequency ω. If the impedance between the power supply and GNI terminals of the LSI chip 2 changes in synchronization with ω, the power supply current of L8'I changes with a certain time constant in accordance with the change in impedance. Then, due to the resistance 1 of the package lead portion, the change in current causes a change in voltage at the power supply terminal. On the other hand, if the rate of change of the power supply is set to 7, the voltage at the power supply terminal will vary greatly depending on both the power and the power supply.
又、前記ωが非常に大きくなると前記インダクタンスＬ
のインピーダンスが大きくなり、゛コンデンサー３の効
果がなくなシミ原電流の変動がそのまま電源端子の電圧
変動として表われる。Moreover, when the ω becomes very large, the inductance L
The impedance of the capacitor 3 becomes large, and the effect of the capacitor 3 is lost, and fluctuations in the original current of the stain directly appear as voltage fluctuations at the power supply terminal.
次に１本発明によるパッケージを使用した場合を考える
。第２図（ａ）はデエアルインラインのセラミックパッ
ケージに適用した場合の応用例を示している。同図にお
いて、４はチップコンデンサー、５はチップコンデンサ
ーの１ｌｔ４Ｌ！： Ｉ Ｃパッケージのステッチを接
続する庭めのはんだ、６はＬＳＩテップＶＤＤ、 Ｖｓ
＋ｓはそれぞれ電源パッドとＧＮＤパッドを表わしてい
る。同図（ｂ）は同図（ａ）の等価回路である。ＬＳＩ
自身の動作によって電源電流が変化するところまでは前
記従来の場合と同じであるがこの電源電流の変化は第２
図に示されたコンデンサー４によって吸収され、前記イ
ンダクタンスに我われる電流変化は非常に小さくなる。Next, consider a case in which a package according to the present invention is used. FIG. 2(a) shows an example of application to a dead air in-line ceramic package. In the same figure, 4 is a chip capacitor, and 5 is a chip capacitor 1lt4L! : The solder for connecting the stitches of the IC package, 6 is the LSI tip VDD, Vs
+s represents a power supply pad and a GND pad, respectively. FIG. 5(b) is an equivalent circuit of FIG. 1(a). LSI
The point where the power supply current changes due to its own operation is the same as in the conventional case, but this change in power supply current is caused by the second
The current change absorbed by the capacitor 4 shown in the figure and passed through the inductance becomes very small.
したがって、ＬＳＩチップの電源端子に表われる電圧変
動が小さくなる。Therefore, voltage fluctuations appearing at the power supply terminal of the LSI chip are reduced.
この様に本発明によるＩＣパッケージを使用する事によ
υ、Ｌｉ９Ｉ自身の動作に起因するＬＳＩチップの電源
端子の電圧変動は無祝出米、ＬＳＩのよシ安定な動作が
可能になる。これは特に自身の動作による電源電圧変動
を受は易い０ＭＯ８ＬＳＩや、ディジタルアナログ混在
ＬＳＩ用のＩＣパッケージとして効果的である。As described above, by using the IC package according to the present invention, the voltage fluctuations at the power supply terminal of the LSI chip caused by the operation of Li9I itself can be avoided, and the LSI can operate more stably. This is particularly effective as an IC package for 0MO8LSI, which is susceptible to power supply voltage fluctuations due to its own operation, and digital/analog mixed LSI.
次に本発明によるＩＣパッケージをＣＭＯＳディジタル
ＬＳＩに適用した場合の実施例について説明する。ＣＭ
Ｏ８ＬＳＩｔ１論理ゲートがスイッチングする時にのみ
電源電流が流れる。特にチャンネル幅の大きいトランジ
スタがスイッチングする時にはかなシ大きな過渡電流が
流れる。第３図（ａ）はこの電流波形を同図（ｂ）は従
来のＩＣパッケージを使用した時のＶＤＤ端子の電圧波
形、同図（Ｃ）は本発明のＩＣパッケージを使用した時
のｖＤＤ端子の電圧波形ｆ：表わしている。Next, an embodiment in which the IC package according to the present invention is applied to a CMOS digital LSI will be described. CM
Power supply current flows only when the O8LSIt1 logic gate switches. Particularly when a transistor with a large channel width switches, a large transient current flows. Figure 3(a) shows this current waveform, Figure 3(b) shows the voltage waveform at the VDD terminal when using the conventional IC package, and Figure 3(C) shows the voltage waveform at the vDD terminal when using the IC package of the present invention. The voltage waveform f: represents.
この様に本発明によるＩＣパッケージを使用する事によ
り、ＬＳＩ自身の動作に起因するＶＤＤ端子の電圧質＃
を抑え、前記ＬＳＩの安定な動作が可能になる。In this way, by using the IC package according to the present invention, the voltage quality of the VDD terminal caused by the operation of the LSI itself can be improved.
This enables stable operation of the LSI.
第１図（ａ）は従来のＩＣパッケージにコンデンサーを
外付けした例、第１図（ｂ）は第１図（ａ）の等価回路
、第２図（ａ）は本発明のＩＣパッケージ例、第２図（
ｂ）は第２図（ａ）のＩＣパッケージの等価回路、第３
図（ａ）はＣＭＯ８Ｌ８１の電源電流波形の一例、第３
図（ｂ）は第３図（ａ）の電流が流れる０ＭＯ８ＬＳＩ
に従来のＩＣパッケージを使用した時のＶＤＤ端子の電
圧波形、第３図（Ｃ）は本発明のＩＣパッケージを使用
した時のＶＤＤ端子の電圧波形、である。
なお図において、１・・・・・・パッケージリード部の
抵抗、２・・・・・・ＬＳＩチップ、３・・・・・・コ
ンデンサー、４・・・・・・チップコンデンサー、５・
・・・・・はんだ、６・・・・・・ＬＳＩチップ、Ｌ・
・・・・・パッケージリード部のインダクタンス、であ
る。
（ａ）
第１図
（久）
第 ２ 図
ＤＤ
第３図FIG. 1(a) is an example of a conventional IC package with a capacitor externally attached, FIG. 1(b) is an equivalent circuit of FIG. 1(a), and FIG. 2(a) is an example of an IC package of the present invention. Figure 2 (
b) is the equivalent circuit of the IC package in Fig. 2(a);
Figure (a) is an example of the power supply current waveform of CMO8L81.
Figure (b) is a 0MO8LSI in which the current shown in Figure 3 (a) flows.
3(C) shows the voltage waveform of the VDD terminal when using the conventional IC package, and FIG. 3(C) shows the voltage waveform of the VDD terminal when using the IC package of the present invention. In the figure, 1... Resistor of package lead part, 2... LSI chip, 3... Capacitor, 4... Chip capacitor, 5...
...Solder, 6...LSI chip, L.
...Inductance of the package lead section. (a) Figure 1 (Ku) Figure 2 DD Figure 3
Claims (2)
の内部に容ｔを形成する手段と、前記容量の一方の電極
を前記ハラケージの電源用ステッチに接続する手段と、
他の一方の電極を前記パッケージの接地用ステッチに接
続する手段とを有する□ａｔ特徴とするＩＣパッケージ
。(1) #? In a package for a conductive integrated circuit, means for forming a capacitor T therein, and means for connecting one electrode of the capacitor to a power supply stitch of the Hara cage;
and means for connecting the other one of the electrodes to a grounding stitch of the package.
する特許請求の範囲第（１）項に記載のＩＣパッケージ
。(2) The IC package according to claim (1), wherein the capacitor is a chip capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56176034A JPS5877251A (en) | 1981-11-02 | 1981-11-02 | Ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56176034A JPS5877251A (en) | 1981-11-02 | 1981-11-02 | Ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5877251A true JPS5877251A (en) | 1983-05-10 |
Family
ID=16006562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56176034A Pending JPS5877251A (en) | 1981-11-02 | 1981-11-02 | Ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5877251A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5032892A (en) * | 1988-05-31 | 1991-07-16 | Micron Technology, Inc. | Depletion mode chip decoupling capacitor |
| US5687109A (en) * | 1988-05-31 | 1997-11-11 | Micron Technology, Inc. | Integrated circuit module having on-chip surge capacitors |
| US6114756A (en) * | 1998-04-01 | 2000-09-05 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit leadframes |
| US6124625A (en) * | 1988-05-31 | 2000-09-26 | Micron Technology, Inc. | Chip decoupling capacitor |
| US6414391B1 (en) | 1998-06-30 | 2002-07-02 | Micron Technology, Inc. | Module assembly for stacked BGA packages with a common bus bar in the assembly |
-
1981
- 1981-11-02 JP JP56176034A patent/JPS5877251A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448628B2 (en) | 1988-05-31 | 2002-09-10 | Micron Technology, Inc. | Chip decoupling capacitor |
| US5687109A (en) * | 1988-05-31 | 1997-11-11 | Micron Technology, Inc. | Integrated circuit module having on-chip surge capacitors |
| US5032892A (en) * | 1988-05-31 | 1991-07-16 | Micron Technology, Inc. | Depletion mode chip decoupling capacitor |
| US6124625A (en) * | 1988-05-31 | 2000-09-26 | Micron Technology, Inc. | Chip decoupling capacitor |
| US6184568B1 (en) | 1988-05-31 | 2001-02-06 | Micron Technology, Inc. | Integrated circuit module having on-chip surge capacitors |
| US6265764B1 (en) | 1998-04-01 | 2001-07-24 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit lead frames |
| US6396134B2 (en) | 1998-04-01 | 2002-05-28 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit lead frames |
| US6114756A (en) * | 1998-04-01 | 2000-09-05 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit leadframes |
| US6531765B2 (en) | 1998-04-01 | 2003-03-11 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit lead frames and method |
| US6730994B2 (en) | 1998-04-01 | 2004-05-04 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit lead frames and methods |
| US6563217B2 (en) | 1998-06-30 | 2003-05-13 | Micron Technology, Inc. | Module assembly for stacked BGA packages |
| US6414391B1 (en) | 1998-06-30 | 2002-07-02 | Micron Technology, Inc. | Module assembly for stacked BGA packages with a common bus bar in the assembly |
| US6838768B2 (en) | 1998-06-30 | 2005-01-04 | Micron Technology Inc | Module assembly for stacked BGA packages |
| US7279797B2 (en) | 1998-06-30 | 2007-10-09 | Micron Technology, Inc. | Module assembly and method for stacked BGA packages |
| US7396702B2 (en) | 1998-06-30 | 2008-07-08 | Micron Technology, Inc. | Module assembly and method for stacked BGA packages |
| US7400032B2 (en) | 1998-06-30 | 2008-07-15 | Micron Technology, Inc. | Module assembly for stacked BGA packages |
| US7408255B2 (en) | 1998-06-30 | 2008-08-05 | Micron Technology, Inc. | Assembly for stacked BGA packages |
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