JPS5876946A - Digital operating device - Google Patents

Abstract

PURPOSE:To reduce the delay in propagation and to speed up carry propagation, by taking a gate corresponding to an even number order bit of a logical gate chain as a twin pair gate for the gate corresponding to an odd number order bit. CONSTITUTION:A carry propagation path of an incrementor/decrementor is formed by connecting NAND gates 12, 14 and NOR gates 13, 15 being twin pair gates of the gates 12, 14 alternately at each bit. The propagation delay time of the carry propagation path is expressed as (n-2)DELTAT and quickened, where DELTAT is the propagation delay time for the NAND gates and inverters. A decrement/ increment selection terminal DEC performs increment when the terminal is a low logical level and decrement when a high logical level.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an adder, an ALU (arithmetic logic unit),
The present invention relates to a digital data arithmetic device such as an incrementer/decrementer, and particularly relates to a digital arithmetic device that propagates a carry (borrow) signal from lower bits to upper bits at high speed.

FIG. 1 shows an example of a conventional incrementer/decrementer circuit. This relates to a 6-bit digital arithmetic device.

FIG. 1 shows an example of a conventional incrementer/decrementer circuit. This is 6-bit digital data x6---
--- Input xo (x5: MSB, xo: LSB) and add +1 or -1 to data y6...
yo (76: MOB, yo: LSB).

DEC! Decrement/increment selection terminal; increment when '0# (low logic level), '1
'' (high logic level) to perform a decrement operation.

1~s, y~11HtXOR (exclusive OR) gates, 12~16 are NAND gates, 6°16~1
9 is an inverter. +1 or -1 result y...
. . . Among yo, yo is the fastest to determine its value, and conversely, the most significant bit, y6, is the slowest. In other words, when adding +1, the value of yn is determined by whether or not a carry occurs from the 1st bit when adding 1 to In-1...''o. Therefore, the determination of the result for the upper bit is delayed.The propagation path of this carry is the part surrounded by the dotted line in Figure 1.The structure of this propagation path is an AND chain, which includes a NAND gate and an inverter. One set,
The configuration is such that four sets of these are connected in series. in this case,
If the propagation delay time of the NAND gate and the inverter are both ΔT, then in the case of 5n bits, the delay time of the can path surrounded by the dotted line is Fi8ΔT, and the propagation delay is Q(n-2)ΔT.

This delay time determines the maximum propagation delay time in FIG.

The present invention has been made to significantly reduce this maximum propagation delay.

FIG. 2 shows an embodiment of the present invention. FIG. 2 shows an improved version of the incrementer/decrementer shown in FIG. 1, and the functions are exactly the same, but the maximum propagation delay time is reduced to about half. In Figure 2, the AND in the dotted line in Figure 1
Instead of a chain, NAND gates (12, 14) and NOR gates (13, 15), which are dual gates thereof, are alternately connected for each bit. Therefore, the propagation delay time of the carry propagation path in the dotted line in Figure 2 is 4ΔT, and when considered in terms of n bits, it becomes (n-2)ΔT, which is reduced to half of that in Figure 1. As a result, a high-speed incrementer/decrementer can be realized. The circuits outside the dotted line in Figure 2 are even numbered pips (!2.) compared to the circuit in Figure 1.
``4) bit processing circuit (for example, x2vc vs. 8 (7) It gets faster.

It should be made clear here that the embodiment, ie, the circuit of FIG. 2, has the same logic as that of FIG. 1.

The difference between Fig. 2 and Fig. 1 is that even number bi-nod (!
2. ! 4) It's only the eye part, and x4 → y4 (the path from input x4 to result y4) is exactly the same as x2 → y2! It is sufficient to prove that the path 2→y2 is the same as that in FIG. That is, it is sufficient if 82 in FIG. 2 is the same as B.

As is clear from both figures, A in FIG. 1 and A in FIG. 2 are the same signal. 2 in Fig. 2 and 1 in Fig. 1 are respectively expressed by the following formulas.

B2=A+(x2■DEC)---(1).

B, = A e (x2■DEC) --------(2)
According to De Morgan's law, since equations (1) and +2) are the same, B2==B. Similarly, y2 in FIG. 2 is shown as y2=AΦx2, and Oy2 in FIG.
2=jlΦx2=AOx2, so both o y2 are equal.

From the above explanation, we can see that, like a two's complementer or an adder/subtractor, the carry (or borrow) from the lower bits propagates to the upper bits with a diameter of 1! In a circuit having Is-, the carry propagation path is NAND-NORf x -7 (also n N
If you use OR-N A N D f knee 7),
Maximum operating speed can be obtained with ripple carry one-way type.

As explained above, according to the present invention, carry propagation can be made high-speed when performing digital data operations such as a complementer and an adder, so that a high-speed ripple-carry type digital arithmetic device with a small number of gates can be used. can be realized.

FIG. 2 is a specific circuit configuration diagram of an embodiment of the present invention.

1-s, 7-11-, ---1i: XOR gate, 12-16...NAND gate.

Claims (2)

[Claims] (1) A bit processing circuit that is provided corresponding to each bit of digital input data having a plurality of bits and that performs arithmetic processing on the corresponding bit, and a logic gate that runs from the lower bit to the upper bit of the input data. - A control circuit that includes a chain and generates a control signal for controlling the bit processing circuit, wherein the gate corresponding to the even-numbered bit of the logic gate-chain is a dual gate of the gate corresponding to the odd-numbered bit. A digital arithmetic device characterized by: (2) Claim 1, characterized in that the gate corresponding to the even numbered bit of the logic gate chain is a NAND gate or a NOR gate, and the gate corresponding to the odd numbered bit is a NOR gate or a NAND gate. The digital arithmetic device/