JPH01266627A - Logic circuit - Google Patents

Abstract

PURPOSE:To obtain a high integrated logic circuit by a simple circuit by using the uppermost bit of a unit circuit as multi-input AND. CONSTITUTION:Input data In-In+3 are inputted from the 1 side at every N bits, and On-On+3 are outputted from the 2 side. A carry input Cn-1 is inputted from the 3 side, and outputted to Cn+3 of the 4 side. When this unit circuit is a 4-bit unit, the carry propagates successively 3 bits, and the fourth bit goes to multi-input AND. As a result, the circuit constitution is simplified, and also, a delay time caused by propagation of the carry in a unit circuit can be made the same as that of a CLA system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a logical configuration of an incrementer in digital logic.

[Conventional technology]

The incrementer has a function of adding input data and a carry input from the previous stage to calculate an output and a carry to the next stage. A typical example of the conventional incremental method is the carry look ahead (OLA) method.

FIG. 3 shows an example of the conventional N(uXn) CLA method, in which input data is input for each μ bit. +8 comes in from l, λ! 1IOn to On+8 are output. Carry input 0n-1 (C+n when n=0) is input from 3,
It is output to C1+3 of ≠.

In the OLA method, in order to speed up carry calculation, at each bit)n, multiple input AND(
Engineering.・Eng. -1...C1-CIn), the carry output Cn for each bit is calculated at the same time as data input. The fan-in number of the large AND must be suppressed to a maximum of about j bits due to circuit operation constraints.

Therefore,! When configuring an incrementer over a pit, go! One fixed logic circuit as shown in FIG. 3 is created for each pit, and a plurality of basic circuits are constructed in such a way that carries propagate as shown in FIG. t. Therefore, carries propagate sequentially between unit circuits. This incrementer takes the most time when the carry is carried from the least significant bit to the most significant bit. In the case of the CLA method, compared to the carry calculation of the most significant bit within a unit circuit, the lower bits do not directly affect the carry propagation time. Regarding the total amount of hardware, it is equal to the hardware of a unit circuit multiplied by the number of unit circuits, and when constructed using an LSI, it occupies a large area.

〔the purpose〕

An object of the present invention is to propose a logic circuit that is simple and highly integrated.

[Structure of the invention]

To achieve this purpose, a multi-input AND is used to calculate only the most significant bit of the unit circuit at the same time as the carry is input, and a two-input AND is used to sequentially calculate the simple carries of the circuit for the lower bits. This constitutes a CLA type incrementer with a reduced amount of hardware.

〔Example〕

The present invention will be specifically explained below using the drawings.

An example of i/ is shown in FIG. When the unit circuit is in units of μ bits, carries propagate successively up to the third bit, and the second bit is used as a multi-input AND. By doing so, the circuit configuration can be simplified, and the delay time due to carry propagation in the unit circuit can be made the same as in the CLA system. The present invention and CL
The results of comparing Method A are shown in Table/. In this table, the delay time means that in the embodiment of the present invention and OLA type μ-bit unit circuit, when all the input data is / and the carry input is /, the output data will be delayed using the 0MO8 logic simulator with the 73μm rule. This is the result of calculating the delay time to be output. The number of transistors refers to this logic as 0M
When realized in O8, exclusive OR is excluded (
This is a comparison of the total of Pch and N-ch transistors in the AND section.

In the method of the present invention, the carry calculation up to the third bit of each gate is slower than the CLA method, but it catches up with the CLA method in the third bit, so the carry propagation speed of the entire incrementer is the same for both. In terms of the amount of hardware, the invented method is approximately 2 times smaller than the CLA method in terms of area per Hirobit.
0% The number of transistors can be reduced, which is advantageous for high integration.

Table/FIG. 2 shows a second embodiment in which calculation of lower carry propagation is realized by a transfer gate. Another advantage of the present invention is that it is possible to perform carry calculations of lower bits using transfer gates for multi-input AND, which is difficult to implement, and by using transfer gates, it is possible to achieve higher speed than the conventional CLA method.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to configure a highly integrated incrementer with a simple circuit.

By using this in individual circuits and LSIs, it contributes to higher performance of logic devices, LSIs, etc., and is particularly applicable to processor control and arithmetic operations.

[Brief explanation of the drawing]

Figure 1 is an example of the present invention/ Figure 2 is an example of the present invention!
, FIG. 3 shows an example of a conventional CLA system circuit, and FIG. 3 shows the configuration of an incrementer. /...input data, 2...output data, 3...carry input, ≠...carry output,! ...Unit circuit.

Claims (1)

[Claims] In a logic circuit having an N-bit increment function, in which N-bit numerical data is input divided into a plurality of blocks and a carry output terminal of each block is connected to a carry input terminal of another block, the above-mentioned carry The carry output signal supplied to the output terminal is outputted by a multi-input AND gate, and the other carry signals used in the above block are successively outputted by a 2-input AND gate excluding the most significant bit. A logic circuit characterized by comprising each block.