JPS5873092A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To make word lines short and to decrease the access time, by providing a data input/output control circuit at both sides of cell arrays along the direction of data line in the memory cell arrays so as to read out or write data in many-bit at the same time. CONSTITUTION:An RAM of CMOS-IC, for example, has 36 pieces of memory cell arrays 300-335 having the storage capacity of 64-wordX1-bit. One memory cell array 300 includes 64 pieces of static memory cells of 32-rowX2-column and includes 32 word lines and two pairs of data lines 1,100, 1,101. A column switch 400 selecting the data line 1,100 of the array 300 and a column switch 401 of the array 301 are located at counter side of the array and data input/output control circuit 600 and 601 are also located at the counter side of the array. Thus, without producing useless space, the word lines can be decreased and the access time can be quickened.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and particularly to a layout method suitable for a semiconductor memory device in which a large number of data bits are simultaneously written or read.

An example of a layout method for a semiconductor memory device (hereinafter referred to as multi-bit RAM) capable of simultaneous multi-bit reading or writing is shown in FIG. In the same figure, 3
Reference numerals A to 3H indicate memory cell arrays, each of which is composed of a plurality of memory cells (not shown) arranged in a matrix. IIA-IIH are data line groups respectively provided in the memory cell arrays, and 8 is a word line group extended onto the memory cell arrays 3A-3H. In each memory cell array, the selection terminal of the memory cell is coupled to a word line, and the data input/output terminal is coupled to a data line. Reference numeral 7 denotes a group of X address input lines, which are coupled to a group of input terminals corresponding to the first X decoder/word driver circuit. Top IP! The output terminal group of the x decoder/word driver circuit l is coupled to the word line group 8. Reference numeral 9 denotes a Y address input line group 9 which is coupled to a group of input terminals of the Y decoder circuit 2. Output signal group 10 of Y decoder circuit 2
is commonly applied to Y switch circuits 4A, 4B to 4HK provided corresponding to memory cell arrays 38 to 3H, respectively. Data line load circuits 5A-5H are connected to one end of each of data line groups 11A-IIH provided in memory cell arrays 3A-3HK. The other end of the data line is connected to Y switch circuits 4A-48. The Y switch circuit 4A operates in step 5 to select only one set of data lines from the data line group 11A according to the Y decoder output signal group 10 and couple them to the common data line 12AK. The other Y switch circuits 4B to 4H also function similarly. .

6A to 6H are data input/output control circuits, which are composed of a sense amplifier circuit, an input buffer circuit, and an output buffer circuit (not shown). This data input/output control circuit 6
A to 6H are data input lines 13A to 13H when a write operation is instructed by the read/write control signal 15.
138 to the common data lines 12A to 12
A write operation is performed by supplying the signal 1 to
When a read operation is instructed by 5, the data supplied from the memory cell array to the common data line via the Y switch circuit is discriminated by the sense amplifier, further amplified by the output buffer circuit, and sent to the data output lines 14A to 1.
48 and output to the outside.

Naturally, during reading or writing, only one word line is selected from the word line group 8 according to the state of the X address input line.

If 7 lines are used as the X address input line 7, the number of word lines provided in the X decoder/word driver circuit IK is 2.
'=128 lines, and if four lines are used as the Y address input lines 9, the number of sets of data lines provided in each memory cell array will be number 2=16 sets.

The above is the conventional technology, but with this method, 64 words x 36
Although the number of addresses (#) is relatively small for 15 bits,
When attempting to layout a RAM with a large number of simultaneous successive bits (word length), the following disadvantages arise.

Now, in order to enable the storage of 36-bit parallel data signals, it is assumed that 36 memory cell arrays are provided, each inputting and outputting a 1-bit data signal and having a storage capacity of 64 words. do. It is assumed that each half of the 36 memory cell arrays, that is, 18 cells each, are arranged on both sides of the KX decoder/driver circuit l, as in FIG. At this time, the memory cell array for 1 bit (64 words) consists of 8 word lines x 8 data lines.
Various configurations may be used, such as 16 word lines x 4 data lines or 32 word lines x 2 data lines.

However, in a memory array for 1 bit,
As the number of data lines increases, the required length of the word line increases and its capacitance increases, resulting in a longer time for the word line level to rise and slower access time.

79, the memory cell array is configured to have 32 word lines x 2 data lines. In this case, if the size of an l-bit memory cell is, for example, 35βm (length in the word line direction) x 44 μm (length in the data line direction), then the length of the memory cell array for l bits in the word line direction is is 35 μm x 2 = 70 μm. In this case, it is also necessary that data input/output control circuits can be laid out at a pitch of 70 μm in accordance with the memory cell arrays each having a width of 70 μm. However, each data input/output control circuit includes a large number of functional circuits such as the sense amplifier circuit, input puffer circuit, and output puffer circuit as described above, and the constants of the circuit elements used therein are also large. , it is difficult to lay out a width of about 70 μm.

Therefore, as mentioned above, [36 memory cell arrays and 3
When six data input/output control circuits are provided, as shown in FIG.
5 pitch is data human power/output control circuit 600 to 63
It will be limited by the pitch of 5. In other words, it becomes necessary to provide unnecessary space between the memory cell arrays 300 to 335. Further, since the memory cell arrays 300 to 335 cannot be brought close to each other, it becomes difficult to sufficiently reduce the length of the word line, and it becomes difficult to sufficiently shorten the access time.

Therefore, an object of the present invention is to provide a memory cell array that does not create gaps between memory cell arrays even when the length and width in the word line direction of the memory cell array for one bit is smaller than the layout width of the data input/output control circuit. That is, it is an object of the present invention to provide a layout method that can effectively utilize space and shorten the length of word lines.

The problem that occurs in the prior art, as shown in the example in Figure 2, is that the layout width of the data output control circuit corresponding to the bit is larger than the width of the memory cell array for l bits in the word line direction. Nevertheless, this is done because the data input/output control circuits are all placed side by side on the same side of the memory cell array. Therefore, I decided not to do that and instead installed one data input/output control circuit on both sides of the memory cell array.
For example, place them alternately. In this way, if the width is up to twice the width in the word line direction of the memory cell array for one bit, even if data input/output circuits are laid out side by side, there will be no gaps between multiple memory cell arrays. , space can be used effectively and the word line length can be shortened.

Hereinafter, the present invention will be explained in detail based on examples. I will clarify.

FIG. 3 shows a random access memory (
FIG. 3 is a layout pattern diagram of RAM.

Although not limited to memory arrays, the illustrated RAMs are formed by complementary mMO8 integrated circuit technology, each containing 64 words x 1
36 memory cell array 30 with storage capacity of bits
k is set to have a value from 0 to 335.

Therefore, the illustrated RAM has a total of 64 words x 36 words.
K is set to have a storage capacity of 1 bit.

One memory cell array 300 is composed of 64 static memory cells arranged in 32 rows and 2 columns. One memory cell is, but is not particularly limited to, a 6-transistor@CMOS cell, that is, a flip-flop circuit consisting of a pair of complementary inverter circuits whose input terminals and output terminals are cross-coupled to each other, and a pair of transmission gates (MO8).
It is composed of Fg-cho. The pair of transmissions above) MOS
One of the drain and source electrodes of the FET is coupled to a pair of input/output terminals of the flip-flop circuit. The remaining electrodes of the drain electrode and source electrode of the pair of transmission gate MO8FETs are used as a pair of data input/output terminals of the memory cell, and the gate electrode is
Used as a memory cell selection terminal.

The memory cell array 300 includes the plurality of memory cells, 32 words, and two pairs of data lines 1100.
1101. Same line.

The selection terminals of the two memory cells arranged in the k-arrangement are commonly connected to one word line corresponding to the row, and the data lines of each pair of the 32 memory cells arranged in the same column are connected to the word line corresponding to the row. are commonly coupled to a pair of data lines corresponding to the data lines.
A 1-bit memory cell formed on a semiconductor substrate (not shown) has a planar dimension of, for example, 3571 m in the word line direction.
and 44 μm in the data line direction. *Memo j) The plane dimension of the seven-channel array 300 is 70 μm (-35
It is assumed that the distance is 1,408μ (-444m x 32).

Each of the memory cell arrays 301 to 33'5 has the same configuration as the memory cell array 300 described above.

According to this embodiment, 36 memory cell arrays 300
18 memory cell arrays 30, half of ~335
0 to 317 are arranged on one side of the X decoder/driver circuit, and the remaining 18 memory cell arrays 318 to 33
5 is placed on the other side of the X-decoder h driver circuit.

The memory cell arrays 300 to 317 are arranged on the semiconductor substrate without wasting space as described above. That is, the memory cell arrays 300 to 317 are substantially one memory cell array having 32×36 static memory cells arranged in a matrix of 32 rows and 36 columns, 32 word lines, and 36 pairs of data lines. /cIIf
It is made into an i-valent structure.

One memory cell array of 64 words x 1 bit has a size of 70βm x 1408am as described above, so the entire memory cell array 300 to 317 has a size of 1260J.
1m (70J1m x 18) x 1408μ City size k
be done.

Similarly, memory cell arrays 318-335 are arranged on the semiconductor substrate without wasting space.

In this embodiment, a plurality of column switch circuits for selecting two pairs of data lines in each of the odd-numbered memory cell arrays are respectively arranged in one of the memory cell arrays, and in each of the even-numbered memory cell arrays. A plurality of column switch circuits for selecting each of the two pairs of data lines are respectively distributed to the other side of the memory cell array. That is, the column switch circuit 40G for selecting the data line 11''Oo of the lR1st memory cell array 300Q2 pair is connected to one side of this memory cell array 30G (in the 311th memory cell array 3
The column switch circuit 401 for selecting the two pairs of 491101 and 491101 of the second memory cell array 301 is arranged in the lower side of the second memory cell array 301.
01 (on the upper side of the memory cell array 301 in FIG. 3).

Each of the column switch circuits 400 to 434 is composed of a plurality of transmission MO8FETs whose gates are each supplied with a decoded signal from the Y address decoder circuit 2. For example, the column switch circuit 400 is composed of two pairs of data lines 1100 A pair of transmission gate MO5FETs connected between one pair of data lines and a pair of common data lines 1200, and a pair of transmission gates connected #cm between the remaining pair of data lines and the common data 81200. Transmission MO8
It is composed of FET.

, : *m example, the data line load circuits 500, 516, 518, etc. corresponding to the odd numbered memory cell arrays 300, 316, 318, etc. are connected to the other side of these memory cell arrays, although the number is not limited to 41. Even numbered memory cell arrays 301, 317, and 319 are arranged in
Data line load circuits 501, 517, 519 corresponding to etc.
etc. are arranged on one side of these memory cell arrays, respectively. Each of the data line load circuits is composed of, for example, a MOSFET connected Km between the power supply wiring of the circuit and each data line of the memory cell array.

Data human power/output control circuits 600 to 635 are connected to the paired common data @1200 to 1235, respectively. Each of the data input/output control circuits includes, for example, a sense amplifier with a differential circuit configuration in which a pair of differential input terminals are coupled to a pair of common data lines, and an output terminal of the sense amplifier connected to an input terminal. and a manual buffer circuit (none of which is shown) connected to a pair of differential output terminals connected to the pair of common data lines. The manual buffer circuit in each of the data input beat output control circuits 600 to 635 operates on input lines 1300 to 1 when a write operation is instructed by the read/write control signal 15.
A differential data signal corresponding to the data signal being supplied to 335 is supplied to each pair of common data lines. The above-mentioned manual buffer circuit receives the above-mentioned read/write control signal 15.
When a write operation is not instructed by the output terminal, the pair of output terminals are set in a floating state.

When a read operation is instructed by the read/write control signal 15, the output variation circuits in each of the data input/output and control paths 600 to 635 are configured such that when a read operation is instructed by the read/write control signal 15,
Data signal 2 corresponding to the data signal supplied via the sense amplifier is output to output lines 1400 to 1435.

The output buffer circuit is configured, as necessary, so that each output terminal becomes a floating state or a bulk output impedance state 11 when no read operation is instructed by the read/write control signal 4) 15. .

In this embodiment, the width of each data input/output control circuit in the word line direction is 140 μm, or approximately equal to the width of 2 memory cell arrays in the word line direction.

As described above, according to the present invention, even if the width of the memory cell array is smaller than the width of the data input/output control circuit, the layout can be performed without wasting space in the memory cell array, and a highly integrated RAM can be constructed. Tomok, RA with fast access time because the word line length can be shortened
M can be configured.

The invention is not limited to the examples. For example, it is most desirable that the data input/output control circuit be placed on one side of every other memory cell array and on the other side of every other memory cell array, as in the embodiment. , if necessary, may be arranged on one side of every second memory cell array and on the other side of the remaining every second memory cell array. Furthermore, the present invention can be applied not only to RAM but also to ROM.

As mentioned above, according to the present invention 111c, the length and width in the word line direction of the memory cell array for l bits is the pitch).
Even when the layout width is smaller than the layout width of the corresponding data input/output control circuit, it is possible to lay out a high-density memory cell array without creating gaps between memory cell arrays, and shorten the word line length to reduce access time. can be configured with a small amount of memory.

[Brief explanation of drawings]

1 and 2 are RAM layout pattern diagrams, and FIG. 3 is a RAM layout pattern diagram according to an embodiment of the present invention. 1...X address decoder/word driver circuit, 2
...Y address decoder circuit, 300 to 335...
Memory cell array, 400-435... Column switch circuit, 500-535... Data line load circuit, 60
0 to 635...Data human power/output control circuit.

Claims (1)

[Claims] A semiconductor memory device capable of simultaneously reading or writing multi-bit data, in which data input/output control circuits are arranged on both sides of the memory cell array with the memory cell array in between along the data line direction in the memory cell array. A semiconductor memory device characterized by: