JPS5872787U - Input level and power supply voltage reduction status display circuit - Google Patents
Input level and power supply voltage reduction status display circuitInfo
- Publication number
- JPS5872787U JPS5872787U JP16847881U JP16847881U JPS5872787U JP S5872787 U JPS5872787 U JP S5872787U JP 16847881 U JP16847881 U JP 16847881U JP 16847881 U JP16847881 U JP 16847881U JP S5872787 U JPS5872787 U JP S5872787U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- supply voltage
- display circuit
- voltage reduction
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Facsimiles In General (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来例を示す図、第2図は本考案の一実施例を
示す図である。
3・・・・・・増幅器、4・・・・・・表示回路、6・
・・・・・電源電圧減少状態検出回路。FIG. 1 is a diagram showing a conventional example, and FIG. 2 is a diagram showing an embodiment of the present invention. 3...Amplifier, 4...Display circuit, 6.
...Power supply voltage decrease state detection circuit.
Claims (1)
続された表示回路と、該表示回路と並列に接続された電
源電圧減少状態検出回路とを備え、前記表示回路及び前
記電源電圧減少状態検出回路に印加される電源電圧が充
分高い場合には、前記電源電圧減少状態検出回路をオフ
すると共に前記2表示回路にて前記増幅器へ印加される
入力信号のレベルを表示するようにし、電源電圧が一定
値以下に減少した場合には、前記電源電圧減少状態検出
回路をオンし、その出力を前記増幅器の出力に重量して
前記表示回路に印加することにより前記表示回路を飽和
状態となし、以って前記表示回路にて電源電圧が減少し
たことを表示するようにした入力レベル兼電源電圧減少
状態表示回路。An amplifier to which an input signal is applied, a display circuit connected to an output end of the amplifier, and a power supply voltage reduction state detection circuit connected in parallel with the display circuit, the display circuit and the power supply voltage reduction state detection circuit being connected in parallel to the display circuit. When the power supply voltage applied to the detection circuit is sufficiently high, the power supply voltage decrease state detection circuit is turned off and the level of the input signal applied to the amplifier is displayed on the second display circuit, and the power supply voltage is decreases below a certain value, the power supply voltage decrease state detection circuit is turned on, and its output is added to the output of the amplifier and applied to the display circuit, thereby bringing the display circuit into a saturated state; Therefore, the input level and power supply voltage reduction state display circuit is configured to display that the power supply voltage has decreased in the display circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16847881U JPS5872787U (en) | 1981-11-11 | 1981-11-11 | Input level and power supply voltage reduction status display circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16847881U JPS5872787U (en) | 1981-11-11 | 1981-11-11 | Input level and power supply voltage reduction status display circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5872787U true JPS5872787U (en) | 1983-05-17 |
Family
ID=29960527
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16847881U Pending JPS5872787U (en) | 1981-11-11 | 1981-11-11 | Input level and power supply voltage reduction status display circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5872787U (en) |
-
1981
- 1981-11-11 JP JP16847881U patent/JPS5872787U/en active Pending
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