JPS5871734A - Counter circuit - Google Patents

Abstract

PURPOSE:To obtain a counter circuit which is capable of a high-speed working with a small number of gates, by constituting a replacing circuit in a counter consiting of n bits of a shifting means for (n-1)bits and an exclusive OR circuit for a bit. CONSTITUTION:A count holding register 1 and a work register 3 are driven by the two phase timing signals 101 and 102 which are supplied fon a timing circuit 4. The register 1 is set to its initial state by an initial setting signal 103, and then rewritten to the value of the register 3 by a count replacing signal 104. A count replacing circuit 5 shifts the 2nd-n-th bits, for example, by a bit among (n) count bits of the register 1, and transfers the 1st and n-th bits to the register 3 on the basis of the timing signal 102, in the form of a bit which passed through an exclusive OR gate.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a counter circuit, and particularly to a counter circuit that uses a small number of gates and can be applied when the count number is more important than the count value.

When designing a logic circuit using an LSI, in order to improve the diagnosis rate of the LSI, the logic is usually designed with in-phase transfer prohibited. In that case, the structure of the counter circuit has traditionally been as shown in Figure 1: a register 1 that holds a value, and an increment (or decrement) circuit that performs a plus-one (or minus-one) operation. 2
Then, in order to avoid in-phase transfer of the registers, a timing is generated to constantly supply the work register 3 that holds the result (handle value) calculated in the previous circuit 2, and the 2-invitation tie digits 101 and 102. It consists of Aroyo.

First, the count holding register 1 is set to a predetermined initial state by the initial setting signal 103 using the set input terminal of the register or the work register 3Fi.
, in synchronization with timing 102, always states the value of the current contents of count holding register l plus 1.0 Next, the contents of count holding register 1 are changed to count update signal 104 when turned on. The value held in work register 3 is incremented by 1. In this way, each time the count update signal 104 turns on, the count holding register 1 is incremented by 1.
The count is updated.

Therefore, in conventional counter circuits, in order to obtain the updated count value, a plus one circuit (or a minus one circuit) is used.
Circuit) 2 is essential, and it is necessary to use a large number of gate circuits for calculating plus 1 (or minus 1).

SUMMARY OF THE INVENTION In order to solve these conventional problems, it is an object of the present invention to provide a counter circuit that has a simple configuration by reducing the number of gates and is capable of high-speed counting operation.

In order to achieve the above object, the counter circuit of the present invention has n
A feature of the present invention is that the update circuit for a counter made up of bits is composed of a shift means for n-1 bits and an exclusive OR gate for 1 bit.

In many cases, a counter circuit does not require a count value, but only a count number, depending on its usage.For such applications, the counter circuit of the present invention uses a plus-one circuit, which is conventionally required. The number of gates can be reduced and high-speed Callan F operation can be achieved by using an update circuit consisting of a shift (shift) logic for *-1 bit out of n counting bits and one exclusive disjunction. .

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows the origins of a counter circuit showing one embodiment of the present invention.

As shown in FIG. 2, the counter circuit of the present invention includes a count holding register 1, a work register 3, and a timing generation circuit 4 that constantly supplies two-phase timings 101 and 102. A new count update circuit 6 is provided in place of the l1g circuit.

As in the conventional case, the count holding register 1 is brought into a predetermined initial state by the initial setting signal 103, and its contents are rewritten to the value of the work register 3 by turning on the count update signal 104. In addition, the work register 8 is also set at timing 10, as in the past.
At 8 o'clock in 2, the output of the count update circuit δ, which should become the next count value, is taken in. In this way, each time the count and update signal 104 turns on, the count holding register 1
will be updated.

The count update circuit 6 is one of the two counting bits!
For l-1 bits, it is only necessary to connect the input and output sides to diad one bit at a time, and for the remaining (1) bit, connect one exclusive OR gate to the input and output sides. It consists of

FIG. 3 is a configuration diagram of a count update circuit showing an embodiment of the present invention.

In FIG. 3, al indicates the input corresponding to bit position 1.1. / indicates the updated output corresponding to bit position 1.

As shown in FIG. 3, the updated output h'1(i-1 to (n-
1)) is found by simply shifting the input &yo(i-2~Il), and the remaining one of the update outputs &- is ao
This can be obtained by simply providing one exclusive OR gate 6 of and an. In other words, the count update circuit δ shown in FIG.
is a'1-&1+1 (i-1~(n-1)), a
The updated count value is determined by n-'n■a□. Note that ■ indicates exclusive OR.

Also, by inverting the polarity of either one of the input signals of the exclusive OR, a', -11+, (1-1~(!
l-1)), &---~■a0 can be obtained as the updated count value. In addition, it shows the negation of the exclusive OR of a, ``ala~'' and a.

Note that the exclusive OR gate can obtain complementary outputs simply by reversing the polarity of one of its two inputs, so it is only necessary to select one of the values as the updated count value. . Therefore, if the counter holding register 1 has two outputs, inverted and non-inverted, it is sufficient to select one of the two outputs without adding a new polarity inversion circuit.

III￥4 Figure is an explanatory diagram of the updated value in the case of n-movement in the count update circuit shown in Figure 3. In Figure 4,
For the case of n-4, the initial value of the counter is set to "1111".
shows how the contents of the counter holding register l are updated. &l, &,,i
For iL, ψ is & of the previous value.

It is obtained by shifting & a + & 4 one bit at a time, and the remaining a is obtained by exclusive ORing the previous values 10 and 14.

In the case of n-nutrient, after counting from 1 to 16 as shown by the arrow, it returns to the initial @"1ill", so 1
It can be used as a counter circuit up to 6.
Note that if the initial value is set to "0000", a loop will be returned to the original value, so it is necessary to use a value other than this as the initial value.

Also, as is clear from Figure 4, the count values from 1 to 15 change to any value without being sequentially increased by plus 1 or minus 1. It is extremely advantageous to use this method when emphasis is placed on

FIG. 5 is a diagram showing the maximum count number relative to the number of bits in the counter circuit of the present invention.

In the case of counting bits "-2p n"'-3 and 11-4, it is possible to count the same number of combinations excluding all "0", but in the case of n-6, there are fewer karans) Since there is a value in the middle that loops to itself with a number,
Since the value obtained by dividing these values is used as the initial value, the maximum force and runt number are less than the total number of combinations, 32. zl-f3
For the same reason, all combinations 't! 1.6
The number of counts is less than 4. ◎ FIG. 6 is a block diagram of a color circuit showing another embodiment of the present invention.

FIG. 6(a) shows the case where a parity bit F is added to the contents of the counter circuit, and the count holding register 11
The entire value including the parity bit P is added to the parity checker 14. Conventional counter circuits require a circuit that generates predicted parity based on the value updated by the plus 1 circuit, but the count update circuit 1 of the present invention
In No. 2, the predicted parity pit t can be generated using one exclusive OR gauge, and the number of gates is reduced. That is, as shown in FIG. 6(b), the outputs /, ~a- are obtained from the inputs a0~&, using the method described above, and the updated parity P' is obtained by an and parity p)P. It can be easily obtained by negating the exclusive OR of a certain ψ11ian and the parity pitch P. If you peel it off, the input will be “l l l
l” and parity “I+, the update output is “11
10” and the parity is “0”.

As explained above, in the counter circuit of the present invention, the number of gates can be reduced by subtracting one exclusive OR game (two gates when parity occurs) from the number of gates constituting the conventional plus-one circuit. In addition, since the number of gate stages is reduced, faster counting operation is possible.

Furthermore, when a parity bit is added, a complicated parity prediction MM is not required and the number of gates is further reduced.

[Brief explanation of the drawing]

11s1 is a block diagram of a conventional counter circuit, FIG. 2 is a block diagram of a counter circuit that does not show an embodiment of the present invention, FIG. 3 is a block diagram of a count update circuit that shows an embodiment of the present invention, and FIG. 6 is a diagram illustrating the update operation of the circuit shown in FIG. 3, FIG. 6 is a diagram illustrating the maximum count number with respect to the number of bits of the counter circuit of the present invention, and FIG. 6 is a diagram illustrating another embodiment of the present invention. This is the configuration V of the counter circuit shown in FIG. l: Counter value holding register, 2 Nibras 1 circuit, 3=
Work register, 4 = timing generation circuit, 5: count update circuit, 6, 7: exclusive OR gate, 11: holding register with parity bit added, 12: count update -%, 13: work register, 14 :Parity checker O Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] ■In a counter path having count bits of (plural) bits, a circuit for updating the count value with a shift) child actor for (n-1) bits and an exclusive kII sum gauge for 1 bit! A counter circuit that is characterized by its powerful characteristics. ■The update circuit updates the value of the count bit before update by &t (
1-1~! L), the updated count bit value is a-(1-
1~m), then ``t'''' ``1+1 (1a
m 1 to XL-1), a', - to ■ ai
[Counter circuit described in 0 (to) The update circuit is 1. ', = ,,+1 (t
-1~m-1)&--ζ] "The counter circuit according to claim m, characterized in that (indicates the negation of logical OR) (~In the update circuit, the parity bit before update is P1
When the parity bit after update is P', P'- is PI only P'-a! 2. The counter circuit according to claim 1, wherein the counter circuit is configured such that l■P.