JPS5870557A - Integrated circuit package - Google Patents

Abstract

PURPOSE:To perform checking of internal circuits without increasing a number of terminals by providing the checking terminal to the side at a right angle to a side where terminals are provided on the basis of dual inline. CONSTITUTION:The IC chips C1-C3 are connected with a conductor pattern 17 and are extended to the checking terminal 15 at the side at a right angle to the dual inline terminal 14 with a conductor pattern 16. The chips are connected to the substrate by the face down method. According to this structure, an IC can be checked without increasing a number of terminals 14, an effective terminals can be structured with the same external shape as the ceramic substrate providing the standard number of terminals, resulting in much economical advantage.

Description

[Detailed description of the invention] The present invention relates to integrated circuit IQ packaging.

With the miniaturization and high density of IC and L8I technology, the density of circuits integrated into one IC-4 package is increasing. Although it is sufficient to have terminals, etc., the operation of each circuit block or single circuit element configured between input and output cannot be seen from the external terminal. This problem of not being able to see the operation from external terminals is becoming more serious as the integration density increases. These become even more of a problem for manufacturers of integrated circuits. Particularly in multi-chip type cages consisting of multiple chips, it is essential to be able to identify defective chips in order to avoid the disadvantage of having to discard all other chips and 14 cages due to a defect in one chip. However, in the conventional dual in-line type 99 cage, if an attempt is made to solve this problem, the number of lead-out terminals for the internal circuit increases, resulting in a package with a significantly large number of terminals and a large size.

Figure 1 is an example of a telephone exchange subscriber circuit consisting of circuits L1 and L2 in which switches 81 to S5 are configured on lines A and B, where 1 to IC are the main line terminals, and 2 is the control terminal of the switch. It is. C1 to C3 indicate different chips. In the illustrated example, a total of 14 main circuit terminals, 10 control terminals, and 20 terminals for power supply and grounding are required as external terminals. T.A.
I, TBI and TA2. TB2 has switches 82, 83 .
These terminals are used to measure each of the 84 characteristics independently. Including these terminals, a total of (9) external terminals are required.

For example, if a dual in-line type arm cage with four terminals is used as the standard number of terminals, nine new cages would be required for the missing two terminals, which would be uneconomical. Depending on the circuit configuration, a new node cage may be required each time.

Therefore, an object of the present invention is to provide an integrated circuit zf that can test the characteristics of internal circuits and circuit elements that cannot be checked from external terminals without increasing the number of external terminals of a conventional dual in-line type cage. The aim is to provide Kutuji.

That is, the present invention provides a dual in-line integrated circuit package having external terminals on two opposing sides, and a sealed integrated circuit chip connected to the conductor A-turn on the other two sides perpendicular to the side having the external terminals. The present invention relates to an integrated circuit package characterized in that a check electrode is formed.

The present invention will be explained in detail below using specific examples.

FIG. 3 is a sectional view thereof. In the same figure, 10
1 is a ceramic substrate, 11 is its wiring surface, 12 is an integrated circuit chip, 13 is a sealing cap, and 14 is an external terminal.

Reference numeral 15 denotes a check electrode formed on a side perpendicular to the long side of the board on which the terminal 14 is provided in a dual in-line type, and is connected to the sealed internal circuit by a conductor/mother turn 16.

FIG. 4 shows an example of the structure of the conductor/mother turn to the above-mentioned check electrode, and C1 to C3 are C in the circuit block diagram of FIG.
These are integrated circuit chips corresponding to numbers 1 to C3. 17 is a conductor/mother p-y between 7'C1-C2 and C2-C3, 1
6 is the dual in-line terminal 1 from the conductor mother turn 17
This is a conductor/transformer for leading out to the check electrode 15 provided on the side perpendicular to the side of 4. In FIG. 4, illustration of other wiring is omitted.

In the above embodiments, it is connected to the wiring board in a wide-face-down manner.

FIGS. 5 and 6 are a cross-sectional view and a plan view showing another embodiment, in which the chips are connected by wire gating. In the same figure, the dual in-line ceramic substrate is shown.
ρ is the integrated circuit chip, Ru is the sealing cap, Sae is the terminal, 5 is the same check electrode as in the first embodiment, and Han is the conductor arm connecting the check electrode and the integrated circuit chip.
b 2B Shows handing wire.

In the example shown, six check electrodes are provided in a dual-inno-line type/9-type cage with a number of terminals, and a dual-in/in-line type cage with the number of terminals equivalent to the I terminal is constructed.

Electrical contact can be easily and well formed on the surface of the check electrode used in the present invention. - For example, a tungsten-based conductor is plated with nickel and gold, or a solder is applied on top of the plating.

As explained above, according to the present invention, in the dual-in-line type ceramic shoe cage, the check electrode is configured on another side perpendicular to the side on which the terminals are arranged in a dual-in-line manner, so that the number of terminals can be reduced. without increasing
Dual in-line capable of internal checking of integrated circuits
It is also economically advantageous because a large number of effective terminals can be constructed with the same external dimensions as a ceramic substrate with a standard number of terminals. This is particularly effective in multi-chip integrated circuits because the checking electrode allows the chip to be electrically identified from the outside.

Note that the figure is an example, and a structure without the step for airtight sealing shown in FIGS. 3 and 5 may be used.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an example of a circuit configuration to which the present invention is applied, FIG. 2 is a plan view showing an embodiment of the present invention, and FIG.
The figures are a sectional view taken along the line X-X in FIG. 2, FIG. 4 is a plan view showing the wiring surface of FIG. 2, FIG. 5 is a sectional view showing another embodiment of the present invention, and FIG. The figure is a plan view showing the wiring diagram of FIG. 5. 14... External terminal, 15... Check electrode, 16
...Conductor/arm turn, b...Check voltage [26.
...Conductor/Archive/G Agent Masami Akimoto Figure 1 TAI T group Figure 2 Cause 3 Figure 5 Figure 6 Cause 2626゜

Claims (1)

[Claims] In a dual in-line integrated circuit with external terminals on two opposing sides, the conductor/mother turn is connected to the sealed integrated circuit chip on the other two sides perpendicular to the side with the external terminals. An integrated circuit arm cage, characterized in that it has a check electrode formed thereon.