JPS5868720U - AM receiver gain control circuit - Google Patents
AM receiver gain control circuitInfo
- Publication number
- JPS5868720U JPS5868720U JP16362181U JP16362181U JPS5868720U JP S5868720 U JPS5868720 U JP S5868720U JP 16362181 U JP16362181 U JP 16362181U JP 16362181 U JP16362181 U JP 16362181U JP S5868720 U JPS5868720 U JP S5868720U
- Authority
- JP
- Japan
- Prior art keywords
- output
- gain control
- circuit
- receiver
- predetermined level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Circuits Of Receivers In General (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例を示すブロック回路図、第２図は本考案
の一実施例を示すブロック回路図である。
２、ＡＭ受信回路、３：自動利得制御電圧検出回路、４
：アナログ・メモリ、５：電圧発生回路、６：゛チュー
ニング・オブ。 ・FIG. 1 is a block circuit diagram showing a conventional example, and FIG. 2 is a block circuit diagram showing an embodiment of the present invention. 2. AM receiving circuit, 3: Automatic gain control voltage detection circuit, 4
:Analog memory, 5:Voltage generation circuit, 6:゛Tuning of.・
Claims (1)
Ｍ受信機において、 チューニング操作時に所定のレベルの出力を発生し前記
チュー壬ング無操作時に前記所定のレベル以下の出力を
発生する電圧発生回路と、前記ＡＭ受信回路の検波器出
力を平滑して取出す自動利得制御電圧検出回路と、 前記チューニング操作時に前記電圧発生回路の前記所定
のレベルの出力が制御信号として印加された塙合は前記
検出回路からの前記自動利得制御電圧を通過させて出力
し且つレベル変動する前記自動利得制御電圧を常に更新
しながら記憶し、前記チューニング無操作時に前記電圧
発生回路の前記所定のレベル以下の出力が制御信号とし
て印加された場合は前記記憶された電圧値を出力するア
ナログ・メモリとを有し、このアナログ・メモリの出力
が前記ＡＭ受信回路の被制御高周波増幅器の利得を制御
することを特徴とするＡＭ受信機の利得制御回路。
゛[Claims for Utility Model Registration] A that extracts a signal by receiving and processing a single-width modulated carrier wave
In the M receiver, a voltage generating circuit generates an output at a predetermined level during a tuning operation and generates an output below the predetermined level when the tuning operation is not performed, and a detector output of the AM receiver circuit is smoothed. An automatic gain control voltage detection circuit to be extracted and a connector to which the output of the predetermined level of the voltage generation circuit is applied as a control signal during the tuning operation pass the automatic gain control voltage from the detection circuit and output it. The automatic gain control voltage whose level fluctuates is constantly updated and stored, and when an output of the voltage generation circuit below the predetermined level is applied as a control signal when the tuning operation is not performed, the stored voltage value is stored. 1. A gain control circuit for an AM receiver, characterized in that the output of the analog memory controls the gain of a controlled high frequency amplifier of the AM receiver circuit.
゛
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16362181U JPS5868720U (en) | 1981-10-31 | 1981-10-31 | AM receiver gain control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16362181U JPS5868720U (en) | 1981-10-31 | 1981-10-31 | AM receiver gain control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5868720U true JPS5868720U (en) | 1983-05-10 |
Family
ID=29955911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16362181U Pending JPS5868720U (en) | 1981-10-31 | 1981-10-31 | AM receiver gain control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5868720U (en) |
-
1981
- 1981-10-31 JP JP16362181U patent/JPS5868720U/en active Pending
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