JPS5868368A - Picture recording device - Google Patents

Abstract

PURPOSE:To obtain fine recording density by connecting a recording head to a circuit board through a flexible cable and the circuit board to a recording control circuit through a flat cable, and thus obtaining a lightweight recording device while stabilizing a main scan, etc. CONSTITUTION:A carriage 18 mounts a thermal recording head 23 and reciprocates in main scan directions, and the head 23 faces recording paper at the top of the carriage 18. On this carriage 18, a circuit board 19 equipped with a driving circuit for the head 23 is mounted, and the head 23 is connected to the board 19 by a flexible cable 22 through a connector 21. The board 19 is connected to a recording control circuit 25 through a flat cable 25. Thus, the weight of the recording head is reduced to stabilize a run of the carriage, and the recording head is detached from the carriage easily.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image recording device f that is effective for recording devices of facsimile machines, etc., and particularly relates to an improved mechanism around the recording head.

Image recording devices such as facsimile machines are equipped with a recording head arranged vertically for multiple dots (multiple recording lines), and main scan the recording head in the horizontal direction perpendicular to the feeding direction of the recording paper. Sub-scanning is performed in the vertical direction, which is the paper feeding direction and the dot arrangement direction.

Such an image recording apparatus is required to have a precise recording density of 7.7 donots/-, and therefore there is a strong demand for the recording means to be lightweight and to have stable running during main scanning and the like.

Therefore, in the present invention, each structure of the recording means has been devised so that it can run stably by reducing the weight of the carriage, and it is also constructed so that repairs of each component of the recording means can be made convenient. It is.

In particular, the carriage means on which the recording head that performs main scanning is mounted is equipped with a circuit board equipped with a recording head drive circuit, and the connection between this circuit board and the recording head is made so that the recording head part can be attached to and detached from the carriage. A connector is provided on the substrate side so that the recording head can be moved freely, and the flexible cape is led out from the recording head and connected to the connector.

This reduces the weight of the recording head and allows the recording head to be easily removed from the carriage for repairs, etc., and the head can be easily replaced.In addition, the number of signal lines between the carriage means and the image processing means can be reduced. The connecting cable between the carriage means and the image processing means is made small and flexible to allow smooth movement of the carriage means in the main scanning direction.

A facsimile machine equipped with an image recording device of the present invention will be described below.

Figure 1 shows a line control unit called 1i1NCU in Figure 1 with the image recording unit of the facsimile machine removed.
Controls connection of public line to modem 2. The modem 2 converts the analog information transmitted from the other station into digital information and supplies it to the image processing device 3.

The image processing device 3 performs processing according to the procedure determined by the CCITT recommendations. In addition, the processing device 3 uses the image information transmitted from the other station, whether it is accurate (hereinafter referred to as fine information) or coarse density (hereinafter referred to as standard information). The determination is made based on the control information or the operation switch of the receiving station, and the flag 8 is controlled.

In this case, if it is fine information, flag 8 [F]
■If the specific output is standard information, it will be output.

4 is a memory for storing the transmitted image information;
It has a capacity that can store two blocks of information for six lines.

Reference numeral 5 denotes a recording control circuit, which outputs 32 bits of image information in the vertical direction to the recording device 7 in accordance with a synchronization signal from the clock generation circuit 6.
Output to heserial. The details of the recording control circuit 5 are specifically shown in FIG.

The clock generation circuit 6 supplies a plurality of synchronization signals to the image processing device 3 and line memory 4 described above.

To explain a little about the processing operation of the image processing device 3 mentioned above, image information transmission according to the CCITT recommendation is as follows.
First, before transmitting image information, synchronization with the other station is established, and image information is transmitted line by line based on this synchronization signal (6 Hz). On the other hand, the receiving station sequentially stores each line in the line memory 4 in accordance with the synchronization signal. As mentioned above, the line memory 4 has a capacity of 16 lines (1 line =
It is provided with two memory blocks each having 1728 bits) and is used in a dual buffer system.

In addition, the above-mentioned recording device 7 performs main scanning (main scanning) by moving a recording head (thermal head) equipped with 32 pit recording elements in the vertical direction in the line direction, and when the line recording is completed, recording is performed while the head returns to its original position. Move the paper vertically (sub-scanning).

The feature of the present invention lies in the configuration of this recording device 7, the details of which are shown in FIG. FIG. 4 showing the characteristic configuration of the present invention will be explained.

18 is a carriage for fixing the thermal head 23, and a guide shirt supported by the side plate 10.11) 12.13
It is movably attached to the

This carriage 18 is linked to a pulse motor that performs main scanning, and this pulse motor guides the carriage 12.
．． It is moved back and forth on 18.

The pulse motor that performs the main scanning moves at a constant speed (moves to the right) in response to a main scanning pulse signal, which will be described later, and moves faster than the main scanning pulse signal (2
(double speed) is returned at high speed by the return pulse.

A thermal head drive circuit (
A circuit board 19 with a circuit board (see FIG.
The thermal head 23 is attached to the head 23 by means of a pin 24.24.

This thermal head 23 is connected to the substrate 19 via a connector 21 with a flexible cable 22. Therefore, the thermal head 23 can be easily removed from the carriage 18 by removing the screw 24 and removing the flexible cable 22 from the connector 21. Further, the substrate 19 is connected to the recording control circuit 5 via a flat cable 25.

The flat cable 25 is flexible and is once fixed to the carriage 18 with a fixture 81 and then connected to the substrate 19. The number of signal lines in this flat cable 25 is preferably as small as possible for stable running (constant speed) of the carriage 18. Therefore, the drive signal is serially supplied to the drive circuit (circuit board 19) of the carriage 18, converted into a parallel signal by the circuit of the board 19, and then supplied to the thermal head 23. This aspect of the configuration will become clearer in the circuit configuration shown in FIG. 8, which will be described later.

26 is fixed to the side plates 10 and 11, and the thermal head 28
This is the back plate facing the

15 and 16 are recording paper guide rollers, and side plates 10° and 11
One end is connected to a sub-scanning pulse motor by a transmission mechanism 30, and moves the recording paper upward. Therefore, the rotatable presser roller 14 is pressed against the roller 15, and the presser roller 17, which is rotatably supported by a shaft 27 that is moved away from the roller 16 by a lever 28, is pressed against the row 216 by a spring 29. has been done.

Therefore, the leading end of the recording paper is pulled out from the rear roll paper of the recording device and is held between the rollers 15 and 14, and then passes between the back plate 26 and the thermal head 23, where it is held between the rollers 16 and 17, and sent out. be done.

The structure of the thermal head 23 described above is shown more clearly in FIG.

In FIG. 5, the thermal head 23 has a thermal head 47 bonded to a substrate 46 (heat radiator), and on the left side of this chip 47 are heating elements 40 (resistors R, R2, . . .
R32) is provided. This resistor R,, R2...
・The layout of R32 is approximately 0.13m as shown in Figure 6.
It has a 32-dot configuration that corresponds to the interval or precision record.

The other end of the heating element 40 (resistor RItR2...R82) is led out as a contact point to one end side of the chip 47, and this contact point is connected to one end of the flexible cable 22 by a fixture 43.

The thermal head drive circuit mentioned in the above description will be explained with reference to FIG. 3. The circuit is constructed on a circuit board 19 mounted on a carriage 18.

A power supply +V is applied to one end of the resistors R, R2, .

The A group is composed of Nant gates GA and -GA3°, and one input of these gates GA to GA32 is connected to each corresponding bit output of the shift register 50, and the other input is connected to a recording control A drive pulse STR from the circuit 5 is input. The shift register 50 sequentially stores the recording data IN from the circuit 5 while being shifted by the shift clock signal HCL.

On the other hand, the B group consists of Nant gates GB1 to GB32, and one input of these gates GB, to GB3° is connected to each corresponding bit output of the shift register 51, and the other input is connected to the recording control A temperature correction pulse 5TR2 output from the circuit 5 is input. The shift register 51 sequentially stores the correction data IN2 from the recording control circuit 5 while being shifted by the shift clock signal HCL. This driving pulse STR is a pulse with a width of approximately 0.4 ms, and 5TR2 is approximately 0.6 ms.
This is a pulse with a width of ms.

Since the correction circuit made up of the B group is a thermal or heat-sensitive recording, the temperature rise time of the heating element differs depending on the presence or absence of previous data, and in order to keep the temperature of the heating element constant and the recording density constant. The correction is made to

Next, the specific configuration of the recording control circuit 5 will be explained in detail with reference to FIG.

61 is a shift register consisting of 17 pits,
It has a 16th bit output terminal 61a and a 17th bit output terminal 61b.

The shift register 61 is sequentially supplied with one column of record data consisting of 16 bits from the line memory 4 and stored therein, and the data from the shift register 61 is transferred to the sofa register 63 (which is made up of 17 pits). Ru.

Further, the shift register 61 outputs an output 61a and an output 61 according to a clock signal supplied from the OR gate 109.
Note that the 16th and 17th bits of the shift register 61 are stored with the same data from the line memory 4. 61 bits are output, and the recorded data of the previous column is stored in the other input. The output of gate groups 101 to 104 is another one consisting of 17 pits.
The data is stored in each corresponding bit of the two shift registers 64.

Therefore, if the shift register 64 receives the record data of one column before, that is, the output from the buffer register 63 is "0".
If the data in the shift register 61 is "1", "1" is stored, and the temperature correction data is stored.

This shift register 64 has the same configuration as the shift register 61. This shift register 64 has an OR gate 10
According to the clock signal supplied from 9, the outputs 64a and 64b are shifted out.

The shift output 61b of the shift register 61 is input to an analog game 115 which becomes valid when the previous flag 8 (see FIG. 1) is fine information [F].

The output of this AND gate 115 is derived as an output IN via an OR gate 117, and is introduced into a shift register 50 (FIG. 3) via a flat cable 25 as shown in FIG.

On the other hand, the shift output 64b of the shift register 64 is input to the AND gate 11B which becomes valid when the fine information [F] is present, and the shift output 64a is input to the AND gate 112 which becomes valid when the standard information (■) is present. The outputs of 118 and 112 are led out as an output N2 via the OR gate 114, and introduced into the shift register 51 (FIG. 3) via the flat cable 25.

Reference numeral 66 is a reference clock generation circuit, and a frequency dividing circuit 6 is used to apply the signal to the shift registers 61, 64, 50, and 51.
7, a frequency dividing circuit 69 that generates drive pulses for a pulse motor to move the carriage 18 (see FIG. 4) in the main scanning direction, and a drive pulse for a pulse motor that moves the recording paper upward in the sub-scanning direction. a frequency dividing circuit 71 that generates
It is supplied to a frequency dividing circuit 70 that generates a synchronizing signal for transmission of each line.

The frequency dividing circuits 67, 69 and 70, 71 described above are constituted by counters, and the frequency dividing circuit 67 further supplies data to a 1-bit 7-lip-flop 68 to generate a pulse with a double period.

In addition, the main scanning frequency divider circuit 69 of the carriage 18 outputs a pulse with a width of about 1.3 ms to the AND gate 126, and outputs a pulse with a period of about b to the AND gate 18.
This latter pulse is the drive pulse of the pulse motor when returning the carriage 18. The frequency divider circuit 71 supplies the pulse number to the counter 72, which outputs 82 pulses. It has an a terminal that outputs "0" when counted, and a b terminal that outputs "0" when 16 pulses are counted.

Further, the frequency dividing circuit 70 generates a synchronization signal for transmission, but synchronization is established with the transmitting and receiving stations before image transmission, and a synchronization signal of 6t(z) is generated regularly.

74 is a heptadary counter, which counts the AND gate 125 color pulses (output of the flip-flop 68) that are enabled by the output "1" from the inverter 122 and the set output of the flip-flop 70 (1/F) 78. 〇When the counter 74 counts 7, it becomes and game 412.
It continues to output "1" until it is reset from 6. When this counter 74 outputs 61'', AND gate 121 and AND gates 113 and 116 become valid.

The output from the AND gate 121 is supplied to the AND gate 110 which becomes valid when fine information is present, and the OR gate 109 outputs a clock signal for a shift operation.

In addition to the hexadecimal counter 74, the pulses of the AND gate 125 mentioned above are supplied to an AND gate 111 that is valid for standard information and an AND gate 118 that is valid for fine information. A shift clock signal is output, and the output of the AND gate 118 is sent to the third
It is output as the shift clock HCL of the shift registers 50 and 51 shown in the figure.

On the other hand, the pulse of the AND gate 124, that is, the pulse of the b period of the pulse of the flip-flop 68, is outputted as the shift clock HCL via the AND gate 119, which becomes valid during standard information.

75 is a 32-decimal counter that counts the shift clock HCL, and a first timer 80 (0,
4m5) and a second timer 81 (0.6ms) which generates a correction pulse 5TR2. These pulses S
TR and 5TR2 are flat cables 25 (see Figure 4)
The output of the 32-decimal counter 75 is not shown, but is supplied to the drive circuit of FIG.
It also serves as a start signal for transferring one column of data in the line memory 4 to the shift register 61.

The output of the frequency divider circuit 70 that generates the transmission synchronization signal (&) Im) described above is supplied to the analog gate 129, and as the other input of this gate 129, it is outputted from the processing circuit when storage of 16 lines is completed. A signal 200 is supplied. The output of this gate 129 is used to set a flip-flop (F//F) 73. Note that it is preferable that the signal 200 be outputted before the 17th synchronizing signal.

The set output of the flip-flop (F/F) 78 enables the AND gate 126 and outputs the main scanning pulse from the main scanning frequency divider circuit 69, resets the counters 74 and 75, and outputs the main scanning pulse through the OR gate 128. supplies drive pulses to the main scanning pulse motor.

Further, the main scanning pulse is supplied to an n-ary counter 76. This n-ary counter 76 is a counter that compensates for the rise of the pulse motor until it reaches a constant speed, and when it counts the n-ary, it outputs "1" and then the AND gate 127 is enabled. The output of the AND gate 127 sets the flip-flop 78, and the AND gate 12 generates a clock.
4,125 is valid. Furthermore, the AND gate 1
The output of 27 is supplied to a main scanning line counter 77 via an OR gate 131.

The main scanning line counter 77 counts the pulses to 1
Terminal a outputs “1” when counting 728 (corresponding to the recording width of A4 size), and terminal b outputs “1” when counting 1728+n (approximately the same as n of the n-ary counter 76 above).
These outputs continue to output '1''.

The output from the a terminal continues to reset the flip-flop (F/F) 78 and serves as a stop control signal for the pulse motor. The output from the b terminal resets the counter 76 and inverts the flip-flop (F//F) 79. This F/
F79 is an instruction signal for the traveling direction of the carriage 18,
When setting, instruct to move to the right.

At the rise of the set output of the flip-flop (F/F) 79, the counter 77 and F/F 73 are reset, and the processing circuit 8 is instructed to complete the main scanning recording;
Data transfer from the line memory 4 to the shift register 61 is stopped. Further, the set output of the F/F 79 enables the AND gate 137, and supplies the sub-scanning pulse from the AND gate 134 or 135 to the sub-scanning pulse motor.

Next, FIG. 8 shows the control operation (FIG. 2) of the device according to the present invention.
This will be explained with reference to the time charts shown in FIGS. 9 and 10.

(1) In the case of fine information This is a record of accuracy, and the flag 8 shown in FIG. 1 is set, and [F] indicating fine information is output.

Then, image information is transmitted from the transmitting station according to the synchronization signal, and this image information is stored for 16 lines in the line memory 4 shown in FIG. Then, a signal 200 is generated from the image processing circuit 3, and the Antogame x2cik side sets l/F73. Further, 16 bits of recording data of the first column are transferred from the line memory 4 to the shift register 61. At this time, please note that the same data is stored in the 16th and 17th bits.

The data introduced into the shift register 61 is first led out to AND gates 101-104.

In the initial stage, the same data as in the shift register 61 is stored in all of the buffer registers 63 and in the reregistration register 4. After this operation, the data in shift register 61 is transferred to shift register 63.

Here, ■ in FIG. 8 indicates the above-mentioned synchronization signal, ■ is a signal 200 indicating the completion of storage, and the signal 2 is placed before the synchronization signal ■.
00 is occurring.

In addition, ■ in FIG. 8 is the signal of the frequency dividing circuit 67, ■ is the signal of the frequency dividing circuit 6B, and ■ is the signal of the frequency dividing circuit 69 (main scanning pulse).
are shown, respectively, where ■ indicates the output of the first class 73, and ■ indicates the output of the I/F 78.

Further, the area [F] shows various signal waveforms when information is received, and the area {circle around (2)} shows various signal waveforms when information is standard.

On the other hand, as mentioned above, when the AND gate 129 opens, the synchronization signal via the gate 129 causes the F/F7 to open.
B is set, thereby making the AND gate 126 valid. As a result, the main scanning pulse (■ in FIG. 8) is output from the gate 126, and this main scanning pulse is output from the counters 74 and 75.
and supplies a driving pulse to the main scanning pulse motor via the OR game 4128.Furthermore, the main scanning pulse is supplied to the n-ary counter 76, and the counter 7
6 counts this.

When the n-ary counter 76 counts the n-ary, the AND gate 127 opens and returns 1'/F78, which is also supplied to the counter 77. The AND gate 125 is enabled by the set output of the 578, and the double period pulse from the gate 17F68 is supplied from the gate 125 to the hexadecimal counter 74, and the AND gate 118 and the OR gate 12
Shift clock HCLf: is output via 0. This shift clock HCL is supplied to the 32-decimal counter 75 and also to the shift registers 50 and 51 shown in FIG.
”, therefore AND gates 113 and 11
6 remains closed, and the recording data IN and correction data IN2 are not output. Therefore, the previous shift registers 50 and 51 are shifted to 7 bits "0" (see SA in FIG. 9).

On the other hand, when the counter 74 counts a hexadecimal value, the AND gate 121 becomes valid and the AND gate 11
8 and +16 are valid.

By opening the AND gate 121, the pulses from the eighth shift clock HCL are transferred to the shift registers 61 and 6 via the AND gate 1-110 and the OR gate 101.
4. And gates 113 and 116
64b of shift register 64 and shift register 6I
61b is supplied, and this is recorded data I.
N and shift registers 5I and 5 as correction data IN2.
0 respectively.

Therefore, the recording data and the correction data are sequentially shifted and stored in the shift registers 50 and 51. They are sequentially shifted as described above, and when the counter 75 counts 32, it outputs "1".

At this time, as is clear from FIG. 9, the shift registers 50 (51) are set to SA, to SA2. 17 bits are “1”. In other words, 17 lines (17 dots) of recording data are set for 16 lines (16 dots) of data.

Signals SA to 5A26 in FIG. 9 indicate the state of each bit of the shift register 50 in FIG. 3, and in this example, the data indicates the state of output "1" at all points.

AND gate 1 is activated by the “1” output of the counter 75.
24 and 125 are closed, the timer 80.81 is activated, and the STR and GBI-G are connected to GA and GA32.
5TR2 is supplied to B82. This STR, and 5T
While R2 is being supplied, each gate opens and the heating element R4
~R3° will be energized and recorded.

Also, if GB - GB, STR, longer width 1
32 Since the pulse 5TR2 is supplied, the corresponding bit stored as "1" in the shift register 51 is energized for a long time to perform correction.

Further, the "1" output of the counter 75 is supplied to the processing circuit 3 to transfer the next column to the shift register 61,
The above operation is repeated for each main scanning pulse.

When all the main scanning lines have been recorded by repeating the above operation, "1" is output from the a terminal of the counter 77, and the F/
Reset F78. For this reason, andgate】24
and 125 closes. Further, the main scanning pulse motor is controlled to stop by the output of the a terminal. After that, when "1" is output from the b terminal of the counter 77, the counter 76 is reset, and the F/F 79 is inverted and set, and the reset output resets the F/F 7B to start the game.
close and stop outputting main scanning pulses.

On the other hand, AND gates 130 and 137 are enabled by the set output of F/F 79, and when this AND gate 180 is opened, a return pulse shorter than the main scanning pulse period output from frequency dividing circuit 69 is supplied to the main scanning pulse motor. Return the carriage at high speed.

Furthermore, when the gate 137 is opened, the sub-scanning pulse motor is caused to feed the paper for 16 lines.

It should be noted here that since the recording consists of 17 lines, the first line of the next 16 lines of recording overlaps with the recording position of the 17th line.

This is to correct the pitch unevenness of the sub-scanning lines by overlapping the recording positions.

It should also be noted that, as is clear from FIG. 9, the center 16 dots (17 dots) of the 32 bits, that is, 5A25 to SA, are used for this fine information. This is because a stable image can be obtained because the center of the recording head is in close contact with the recording paper, and in the case of facsimile, it is also equipped with an image reading device, and in this case, the carriage with the recording head is A reading optical system is also provided. For this reason, since the same synchronization signal is used, when reading the precision, the lens of the optical system is flattened at the center, and a stable reading output can be obtained.

(2) In the case of standard information This is coarse density recording, and the flag 8 in FIG. 1 is reset and a symbol ``■'' indicating standard information is output.

This coarse density recording also operates in the same way as the precision (fine information) recording described above, but especially when the clock signal HCL
1 when is fine information. The difference is that the clock signal has a period of /2.

That is, in FIG. 2, the signal ■ indicating standard information
by Antgame) Ill, 112°115 and 1
19 becomes valid, and the % cycle clock signal output from the AND gate 124 passes through the OR gate 120 to the HC
It is supplied as L to shift registers 50 and 51.

In addition, the clock signal with twice the cycle of the shift clock HCL output from the AND gate 125 is output from the AND gate ■
109 to shift register 61
．． 64 16th bit output 61a of the /ft register 61
is an anime game) +15. IN via or gate 11'l
, O is shifted into the shift register 50 as a signal based on the clock signal.The 16-bit output 64a of the shift register 64 is input to the AND gate 112. The signal is shifted into the shift register 51 as the IN2 signal via the OR gate 114 based on the clock signal.

In this way, the clock signal of the shift register 50.51 is supplied with two pulses for each clock signal of the shift register 61.64.
．． Two bits of data are stored in registers 77 and 50.degree. 51 for one bit of data 64.

Figure 10 shows the shift register 50 in Figure 3 at this time.
In this example, only the 14-bit and 16-bit nodes of the image information are "1", and when the counter 75 in FIG. □, 5A28 and SA8. , SA3
° becomes “1”.

In this way, a coarse density image is recorded with a head having a precision bit array. Note that the operations other than the above are the same as those for the fine information described above, so the details will be omitted.

(3) Other examples When the above fine information is used, the last pinot) (16th bit)
Although the 17th bit is added to the 17th bit so that it overlaps with the beginning of the next line, conversely, 1 bit may be added before the beginning bit and it overlaps with the 16th bit of the previous line. Also, as shown in Fig. 7, a resistor (heating element) 1.5 to 2 times larger than the other dots is placed at the end or beginning R33 of the resistors R1, R2...R8□ of the thermal head. may be formed.

On the other hand, in the shift register 64 in FIG. 2, "1 +1" is recorded only in the newly recorded bits by comparing with the data in the previous column, but conversely, "1 + 1" is stored only in the bits that have already been recorded. and the output pulse of timer 80 is 0.6 m.
s, and the output of timer 81 is 0.4ms shorter than this.
You can also use it as

Further, the timers 80 and 81 are provided with a section for detecting the temperature of the resistor, and the pulse width STR, .
5TR2 may be made variable.

As described above, the image recording apparatus of the present invention includes a carriage means on which a recording head is mounted and moves back and forth in the main scanning direction, and a carriage means provided at the leading end of the carriage means so as to face the recording paper. the recording head, a circuit board mounted on the carriage means and having a recording head drive circuit and connector means on one end side; and a flexible circuit board led out from the recording head side and detachably connected to the connector. This configuration consists of a cable and a flat cable that connects the circuit board and the image processing means side.This makes it possible to reduce the weight of the recording head, contributing to stable running of the carriage, and also making it possible to remove the recording head from the carriage during repairs etc. It can be easily removed, making it easy to replace the head.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing the image recording section of the F7K SHIMI IJ apparatus according to the present invention, FIG. 2 is a block circuit diagram showing the specific configuration of the recording control circuit in FIG. 1, and FIG. 3 is a recording head FIG. 4 is a perspective view showing the configuration of the recording apparatus, FIG. 5 is a diagram showing the specific configuration of the recording head, FIG. 6 is a diagram showing the arrangement of resistors in the recording head, and FIG. The figure is number 6
The arrangement diagrams, FIGS. 8, 9 and 10 showing other embodiments of the figure are time charts for the control operation of FIG. 2. 1: NcU, 2: Modem, 3: Image processing device. 4 second line memory, 5: recording control circuit, 6: clock generation circuit, 7: recording device, 50 and 51: shift register, 61.68 and 64: shift register, 66: reference clock generation circuit, 67.69°70 and 71: Frequency divider circuit, 68 near lip flop, 74! 'l-adic counter, 7
5: 32-decimal counter. 76: n-ary counter, 77: main scanning line counter, 8
0: first timer, 81: second timer. Agent Patent Attorney Aihiko Fukushi

Claims (1)

[Claims] 1. A recording head arranged vertically for a plurality of dots (for a plurality of recording lines) is provided, and this recording head is main scanned in a horizontal direction perpendicular to the feeding direction of the recording paper to print the recording paper. These are the feeding direction and the dot arrangement direction of the head. An image recording device that performs sub-scanning in the vertical direction for recording, comprising: a carriage means on which the recording head is mounted and moves back and forth in the main scanning direction; a leading end of the carriage means is equipped to face the recording paper a circuit board mounted on the recording head and the carriage means and having a drive circuit for the recording head and a connector means on one end side; a flexible cable led out from the recording head side and detachably connected to the connector; and a flat cable connecting the circuit board and an image processing means side.