JPS5866631U

JPS5866631U - semiconductor capacitor

Info

Publication number: JPS5866631U
Application number: JP16143081U
Authority: JP
Inventors: 奥村　益作
Original assignee: 株式会社村田製作所
Priority date: 1981-10-28
Filing date: 1981-10-28
Publication date: 1983-05-06

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来の半導体コンデンサの側面図、第２図は第
１図の半導体コンデンサが表層形の場合の等価回路図、
第３図は第１図の半導体コンデンサが堰層形の場合の等
価回路図、第４図ａおよびｂは夫々本考案に係る半導体
コンデンサの一実施例の正面図および側面図、第５図は
第４図ａおよびｂの半導体コンデンサの構造説明図、第
６図は第４図ａおよびｂの半導体コンデンサが表層形で
ある場合の等価回路図、第７図ａ、　ｂおよびＣは夫々
第４図ａおよびｂの半導体コンデンサが表層形である場
合の製造工程の説明図、第８図ａおよびｂは夫々第４図
ａおよびｂの半導体コンデンサが堰層形である場合の製
造工程の説明図、第９図は第４図ａおよびｂの半導体コ
ンデンサが堰層形である場合の等価回路図、第１０図お
よび第１１図は夫々成型体を円筒形とした場合の実施例
の説明図、第１２図ａ、　ｂ、　　ｃおよびｄは夫々第
１０図および第１１図の半導体コンデンサの製造工程の
説明図、第１３図ａ、　ｂおよびＣは夫々積み重ね形の
半導体セラミ’＋７クコンデンサの製造工程の説明図、
第１４図および第１５図は夫々表層形および堰層形の積
み重ね形の半導体セラミックコンデンサの等価回路図で
ある。２１．２１’・・・成型体、２３．　２３’・・・共通
電極、２４．　２４’、　　２５．　２５’・・・容量
形成電極、２６．２７・・・リード線、Ｃ１□、Ｃ１□
・・・コンデンサ、　　　　−Ｒ，１，Ｒ１□・・・抵
抗、Ｄ工１＋　Ｄ工２・・・ダイオード。Figure 1 is a side view of a conventional semiconductor capacitor, Figure 2 is an equivalent circuit diagram of the surface type semiconductor capacitor in Figure 1,
3 is an equivalent circuit diagram when the semiconductor capacitor shown in FIG. 1 is of weir layer type, FIGS. 4a and 4b are front and side views of an embodiment of the semiconductor capacitor according to the present invention, respectively, and FIG. Fig. 4 is an explanatory diagram of the structure of the semiconductor capacitor shown in Figs. An explanatory diagram of the manufacturing process when the semiconductor capacitors shown in Figures a and b are surface layer type, and Figures 8 a and b are explanatory diagrams of the manufacturing process when the semiconductor capacitors shown in Figures 4 a and b are weir layer type, respectively. , FIG. 9 is an equivalent circuit diagram when the semiconductor capacitors shown in FIGS. 4a and 4b are of a weir layer type, and FIGS. 10 and 11 are explanatory diagrams of examples when the molded bodies are respectively cylindrical. Figures 12a, b, c, and d are explanatory diagrams of the manufacturing process of the semiconductor capacitors shown in Figures 10 and 11, respectively, and Figures 13a, b, and C are illustrations of the manufacturing process of stacked semiconductor ceramic '+7' capacitors, respectively. Explanatory diagram of the process,
FIGS. 14 and 15 are equivalent circuit diagrams of stacked semiconductor ceramic capacitors of surface layer type and weir layer type, respectively. 21.21'... Molded body, 23. 23'... common electrode, 24. 24', 25. 25'... Capacity forming electrode, 26.27... Lead wire, C1□, C1□
...Capacitor, -R,1,R1□...Resistor, D-type 1+ D-type 2...Diode.

Claims

[Scope of utility model registration request]

(1) A first ohmic electrode is provided in a part of a molded body made of semiconductor dielectric material, while a second ohmic electrode is provided in another part of the molded body with a certain gap to the first electrode. A semiconductor capacitor characterized by having electrodes.

(2) Utility Model Registration Scope of the Claim In the semiconductor capacitor according to claim 1, a reduced reoxidation film is formed on the surface of the molded body of the semiconductor dielectric material, and a part of the reduced reoxidation film is removed. A semiconductor capacitor characterized in that an ohmic first electrode is formed in that portion.

(3) Utility Model Registration The semiconductor capacitor according to claim 1, wherein the first electrode is an ohmic electrode and the second electrode is a non-ohmic electrode.