JPS5826201U - delay element - Google Patents
delay elementInfo
- Publication number
- JPS5826201U JPS5826201U JP12064381U JP12064381U JPS5826201U JP S5826201 U JPS5826201 U JP S5826201U JP 12064381 U JP12064381 U JP 12064381U JP 12064381 U JP12064381 U JP 12064381U JP S5826201 U JPS5826201 U JP S5826201U
- Authority
- JP
- Japan
- Prior art keywords
- delay element
- thin film
- substrate
- electrode
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のストリップ線路型遅延素子の斜視図、第
２図は本考案にかかる実施例の遅延素子の断面図、第３
図及び第４図はその使用状態を説明する説明図、第５図
は本考案の遅延素子のリードフレームの平面図、第６図
は第５図のＶＩ−ＶＩ線における断面図、第７図は本考
案の遅延素子のリードフレーム半田付けを説明する説明
図である。
４・・・誘電体基板、５・・・ストリップ線路、６・・
・基板裏面の導体薄膜、７・・・絶縁層、８・・・容量
調整用電極。FIG. 1 is a perspective view of a conventional strip line type delay element, FIG. 2 is a sectional view of a delay element according to an embodiment of the present invention, and FIG.
5 and 4 are explanatory diagrams for explaining the state of use thereof, FIG. 5 is a plan view of the lead frame of the delay element of the present invention, FIG. 6 is a sectional view taken along the line VI-VI in FIG. 5, and FIG. FIG. 2 is an explanatory diagram illustrating lead frame soldering of the delay element of the present invention. 4... Dielectric substrate, 5... Strip line, 6...
・Conductor thin film on the back side of the substrate, 7... Insulating layer, 8... Capacity adjustment electrode.
Claims (1)
路を形成し、該基板の裏面には全面に導体薄膜を形成し
た遅延素子において、基板裏面に形成した導体薄膜の上
に、さらに絶縁層を介して容量調整用の電極を設けたこ
とを特徴とする遅延素子。In a delay element in which a strip line using a magnetic thin film is formed on the top surface of a dielectric substrate, and a conductive thin film is formed entirely on the back surface of the substrate, an insulating layer is further formed on the conductive thin film formed on the back surface of the substrate. A delay element characterized in that an electrode for capacitance adjustment is provided through the electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12064381U JPS5826201U (en) | 1981-08-15 | 1981-08-15 | delay element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12064381U JPS5826201U (en) | 1981-08-15 | 1981-08-15 | delay element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5826201U true JPS5826201U (en) | 1983-02-19 |
Family
ID=29914628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12064381U Pending JPS5826201U (en) | 1981-08-15 | 1981-08-15 | delay element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5826201U (en) |
-
1981
- 1981-08-15 JP JP12064381U patent/JPS5826201U/en active Pending
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