JPS5864699A - Storage circuit device of semiconductor - Google Patents

Abstract

PURPOSE:To eliminate delay due to capacitance coupling, and to realize high- speed operation by setting the threshold voltage of an Y address IGFET for selecting a read signal line by an address signal lower than that of an IGFET for read signal line charging. CONSTITUTION:A memory circuit consists of plural IGFET memories M111- M211, address signal lines Y1, Y2-, and X1, X2- for address specification, Y address IGFETs S11-, and S21- for selecting read signal lines by signals from the address signal lines, and IGFETs QP10-, and QP21- for charging read signal lines connected to read signal lines. The threshold value (2.0V) of the charging IGFETs is set at least 0.5V higher than the threshold value (1.0V) of the Y selecting IGFETs to eliminate delay and to realize high-speed operation due to the capacitance coupling between the Y address lines and read signal lines.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (hereinafter referred to as IGF).
(hereinafter referred to as ET) relates to an integrated semiconductor memory circuit device whose main component is an integrated semiconductor memory circuit device.

In general, in a memory device that uses IGFETt as its main component and is integrated into an integrated circuit, it is necessary to charge and discharge the digit line capacity, which inevitably increases as the capacity increases, and the charging and discharging time is longer than the readout time. It accounts for a large proportion of this. Generally, when a circuit is constructed using N-channel field effect transistors, charging takes longer than discharging.

The ninth digital, digital and digital t-charging period before the readout period (
A commonly used method is to precharge the battery (hereinafter referred to as precharging), and then determine whether the charged state is maintained or discharged at the time of reading. However, the storage device of the above type has the following serious drawbacks.

Hereinafter, as a storage device according to the prior art, an N-channel IG
FET? Example f of a read-only storage device (hereinafter referred to as ROM) will be explained using FIGS. 1 to 3, and its drawbacks will be clarified.

FIG. 1 is a partial circuit diagram of a ROM according to the prior art. In this example, the first readout line 11 is used as a storage element.
1. +12. at3. -Song a21. a! 2. !
! ! , nine memory IGFETs connected in parallel to the Mll
l, Ml 1 +1゜Mus..., M12
1. M122. M1*s・・A-・For memorizing the song I
X address lines Xlt, X2e, X3t, which are connected to the gates of the GFETs and specify the X address; and Y address lines Yl, Y2, which specify the song and the X address; Ys...-
..., the first readout line (alx, asz, a
ss, - inside], (agx.

+22. +2 t...), (), . . . 1 Y for selecting and connecting to the second readout lines bx, bz, . . . by the fcY address signal. Selection IGFET S11. at z, Sl
a,...8zx, S2t, 8 goose 31 songs;...
a friend precharge IGFET Qpr that precharges the first and second readout signal lines; *Qp
A detection amplifier Al that amplifies the potential of I L... and the precharge signal @P, and further the second readout signal lines bx, bz,... by comparing it with a reference potential. ,
It is composed of Ax, . . . -.

The operation of this example is as follows. Figure 3 (a) to (f)
are the precharge signal lines P%XA)”L/
X-ray X, Y address line Y, and first read signal line a.

2 is a diagram showing the voltage waveform of the output 0 of the detection amplifier. Precharge signal line voltage VP (
When the voltage Vx of the X address signal (K1-1) in Figure 3 becomes a high level "H", the voltage Vx (Figure 3 (B)-2) goes to a low level 1.
becomes low and all memory IGFETs are non-conducting @OFF”
Then, the voltage of the X address signal V (Fig. 3 (/'I-
FIG. 2 shows the circuit side of the X address signal where all of the signals 3 and 4) become ``H''. Therefore, IG for precharging
All the FETs are conductive, and the voltage of the first read signal line a (Fig. 3)-5) and the voltage of the second read signal line Vb (Fig. 3 (E)-6) are 1H'
” is charged.

The potential of this 1H" is from the voltage vP of the precharge signal to I
GFET Qpxo, Qptt,...-, Qrzo,...
It is the value obtained by subtracting the threshold voltage of .=;. The output of the detection amplifier is obtained by comparing the comparison reference voltage (Fig. 3 (E)-7) with the voltage vbt of the second read signal line. When the charge signal V becomes @L II, the selected X address signal becomes @
The selected signal for the X address signal remains @H'', and the unselected signal line becomes ``L''.
(IIF3 diagram ← 1-4).

When the X address signal Vx becomes 6H" and the selected storage IGFET is in a conductive state, the voltage 3 on the first read signal line is discharged through the storage IGFET t-, and the voltage decreases. , On the other hand, the voltage Vb of the second read signal line is also applied to the voltage V of the first read signal line through the Y selection IGFET.

The detection amplifier outputs ``L'' when it crosses the comparison reference voltage.

The outline of the operation has been described above, but it has been found that such conventional technology has the following drawbacks. Namely, when the voltage of the first read signal line decreases during the operation during discharge, Y Due to the capacitive coupling between the gate (X address signal line) and source (gl read signal line) of the selection IGF'E'I, the X address signal also decreases (see Figure 3).
/→Refer to the concave part of -3).

Ninth, the Y selection IGFET becomes almost non-conductive, and the discharge of the second read signal line becomes extremely slow. Originally #! The capacitance of the second read signal line is extremely small compared to the capacitance of the read signal line of l, and therefore, if the above phenomenon does not occur, the voltage of the second read signal line will be the same as that of the first read signal line.
The voltage on the readout signal line should drop to about the same level as the voltage on the readout signal line. However, due to the above phenomenon, the voltage on the first read signal line decreases, and the voltage on the second read signal line does not decrease until the difference with the voltage on the X address signal line becomes large. The time required to do so is extremely slow (Fig. 3(f)-8).6 The object of the present invention is to provide a large capacity that eliminates the above-mentioned drawbacks.

The purpose of the present invention is to provide a high-speed storage device.

The memory device fl according to the present invention includes, for example, a memory element group consisting of a plurality of IGFETs connected in a matrix, an X address signal line for specifying an address of the memory element group, an X address signal line, and the memory element group. a plurality of Y-address IGFETs to be selected by a plurality of first readout signals that are selected among them and vary depending on the state of the companion memory element; a second readout signal line selected by the X-address signal; The second storage device includes at least a detection amplifier for amplifying the total detection of the voltage of the second read signal line, and the potential of the first and second read signal lines is before the X address signal is applied. , in the storage device being charged by at least the pre-charging IGFET connected to the first read signal line, the threshold voltage of the pre-charging IGFET is higher than the threshold voltage of the Y-address IGFET. It is characterized by being at least 0.5V higher than the voltage.

Next, one embodiment of the present invention will be described. In order to facilitate comparison with the conventional example, the explanation will be made with reference to the premise of FIGS. 1, 2, and 3.

Note that the basic configuration and operation of the storage device are the same as those of the conventional example, so the explanation will be omitted, and the differences between the two will be mainly explained.

In the embodiment according to the present invention, the precharge IG shown in FIG.
FET Qyso, Qpxt, °=, Qyio, Qy
is.

The threshold voltage of ...... is approximately 2. OV, Y selection IGFET S11. St2.・・・－・82
1. The threshold voltage of ...-... is approximately 1. Set it to Ov. The drawbacks of the prior art can be overcome only by setting the threshold voltage. In other words, the precharge I
() Since the threshold voltage of the FET is increased, the voltage of the first and second read signal lines in the charged state (Fig. 3 (=1.
-105° and Fig. 3 -106)tit compared to the conventional example. OV becomes lower. Therefore, the selected Y
The selection IGFET is applied with the X address signal line voltage without becoming nearly non-conducting, and as the voltage of the first readout signal line decreases, the selection IGFET receives the second readout signal without any time delay. The line voltage also decreases and quickly crosses the comparison reference voltage (Fig. 3 (E)-107), and an output is obtained with an extremely short delay time compared to the conventional example (Fig. 3 (E)-107).
108).

As described in detail above, according to the present invention, it is possible to eliminate the unavoidable large delay due to capacitive coupling between the There is no need to add 7. Note that in the above embodiment, the present invention is applied to a read-only storage device, but it goes without saying that the storage device may be a general read/write storage device. It is.

[Brief explanation of the drawing]

FIG. 1 is a partial circuit diagram of a read-only storage device for explaining storage devices according to the prior art and the present invention.
t1. Mt t! ,...-M121.・・・
-...Mt s 1゜..., M211. . . . is a memory element, 811. St s, ,---. QF t o, QP 11. -”, is IGFET,
Yl, Yl, ・-・. XI, X2. ... is an address signal line, P is a precharge signal line, CC is a power supply, ALl, input 2.・・・・・・
. . . indicates a detection amplifier, and Qt, 02 . . . indicates its output. FIG. 2 is a circuit diagram showing an example of a Y address decoder circuit, and FIGS. 3(A) to 3(F) are diagrams showing voltage waveforms corresponding to each point in FIG. 1. 8 f Figure L Z Figure

Claims (1)

[Claims] A memory element group consisting of a plurality of insulated gate field effect transistors, an address signal line specifying an address of the memory element group, and an insulated gate electric field for Y address that selects a read signal line based on a signal of the address signal line. In a semiconductor memory circuit device including an effect transistor and an insulated gate field effect transistor for charging the read signal line connected to the read signal line, the threshold voltage of the insulated gate field effect transistor for charging the read signal line is , a semiconductor memory circuit device characterized in that the threshold voltage is at least 0.5 volts higher than the threshold voltage of the Y-address insulated gate field effect transistor.