JPS5864693A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To speed up the reading of a memory cell equipped with the 1st FET, the 2nd FET, a read line, a write line, and a word line, by varying only the amplitude of a write signal, which corresponds to write binary information, without changing the polarity. CONSTITUTION:In a 2T cell, a P type area 36 in an electric floating state varies in storage potential through substrate capacitance CB, word-line coupling capacitance CA, a read-line coupling capacit ance CR constituting the storage capacitance CST. A write signal is generated while said potential variation is expected. Namely, a word line voltage VA is so determined that -VAW=-4V during writing operation, and a P channel MOS turns on. Write line voltages are -1V and -4V corresponding to pieces of write information ''0'' and ''1'', but has the same polarity. Consequently, an output signal increase during writing operation, which is speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure for increasing the output signal of a semiconductor memory cell.

A pair of complements! A semiconductor memory constructed of a pair of IFITs has been proposed in Japanese Patent No. 20353 published in 1982. The main advantages of this conventional memory cell (hereinafter abbreviated as 2D cell) are that the size of the memory cell itself can be reduced and that read operations can be performed without destroying the stored information. The advantage is that 2T
This has the advantage of making it easier to read the cell, and increasing the output voltage to the sense amplifier to a certain value as long as it takes time to read. In other words, the memory cell itself was small. However, the 2T cell, which has these advantages, also has some advantages. When attempting to operate stably, there is a problem in that the time required to read the stored information (hereinafter referred to as the "reading time") becomes long. In other words, since it is used as a source follower in the reading operation, it was not possible to obtain a sufficient output with a 2T cell, which has a large substrate bias effect. Another object of the present invention is to eliminate the disadvantages of tJt and to provide a 2T cell with high-speed reading. It is also another object of the present invention to provide a memory cell.
An object of the present invention is to provide a memory cell suitable for a high-speed memory array with a small read line capacitance per memory cell.

Another object of the present invention is to provide a highly reliable memory cell that does not destroy information in other memory cells coupled to a selected read line during reading.

According to the present invention, a first FET of a first conductivity type has a gate electrode, a first current-carrying electrode, a second current-carrying electrode in an electrically floating state, and a substrate region to which a reference potential is supplied;
A gate electrode, a first current-carrying electrode, a second current-carrying electrode to which the reference potential is supplied, and a second conductive electrode that is directly connected to the second current-back electrode of the first FBT and conducts a substrate region that is in an electrically floating state. Yaden 2FET and the above 1st FE when writing
a write line connected to the first current-carrying electrode of the first FET that supplies charge to the substrate region of the second FET through the T and a write signal that sets the threshold voltage of the second FET to either high or low; , a reading line connected to the first electrode of the second FET so as to sense a cutoff signal for detecting the conduction state of the FET during reading;
When writing, supply a signal to turn on only the first FET, and when taking the gun, set the threshold voltage to either high or low. The first P
In a semiconductor memory cell having respective gate electrodes of an ET and a second FET, and a common traditional string, write signals corresponding to write binary information supplied to the write signal have different amplitudes and synchronicity. A semiconductor memory cell is obtained.

Next, a description will be given with reference to the drawings.

Figure 1 is a circuit diagram showing an example of the basic configuration of a 2T cell using M08 transistors.
In the M1 figure, 11, 12, 13, and 16 constitute a p-channel MO8 transistor, and pIJI! is connected to the write line WW', respectively. First energizing electrode 111 gates 4 & 12, n-type base a 13 to which a reference potential is supplied, p-type second energizing electrode @16 in a floating state due to ventilation.
It shows. Similarly, 13.14, To.

16 constitutes an n-channel MO8) transistor, and n'lNl second current-carrying electrodes 13 are each supplied with a reference potential;
The pm substrate region 16 is shown in a floating state with one n-type first conductive electrode connected to the protrusion m RR' and the gate electrodes ts and tL's. As can be seen from Figure 1, the n-type electric current *ls and the 'p-type side 6 are commonly used in both M08 transistors. Person A/ is a word line.

In the 2T cell shown in FIG.
Store progress information. Therefore, when these memory cells are integrated and arranged, the p-type electric current 1i16 must be electrically insulated between each memory cell.

FIG. 2 is an example of a plan view showing the shape of the memory cell shown in FIG. 1 constructed by a silicon gate process. #J
FIG. 3 is a partial cross-sectional view of the memory cell shown in FIG. 2 when cut at the center along the word fIAA. In these figures, 21 and 31 are the pm low resistance diffusion layers that also serve as the first energizing and writing head of the p-channel MO8) transistor, 22 and 32 are the gate part of the transistor,
Now, install the fi type crystal substrate corresponding to 13 in Figure 1, and separate channel MO8) Read transistor 111IR.
25, A is the gate part of the transistor, A is the PM diffusion layer corresponding to FIG. 16, and A is the write line. ``A'' indicates an insulating film that insulates WW' and the word line AA', ``A'' indicates an insulating film that insulates the read line RR and the word line ``A'', and ``Tochi'' indicates a thick insulating film forming an inactive region. Note that the solid line shown in FIG. 2 separates the active region from the inactive region.

The area surrounding the area surrounded by the solid line is the inactive area, and the third
As shown in the figure, the PM diffusion layer is covered with a thick insulating film and has an electrically floating state IIk.That capacitance C1?
Most of this is accounted for by three things: the junction capacitance Cm between the nm substrate, the junction capacitance CI with the vs type low resistance diffusion layer, and the gate capacity Cm with the word line A'.

These capacitances are shown in the equivalent circuit of Figure 1.
ymCA+CB+CM (1) Capacity C
Since IT accumulates a charge corresponding to stored information, it is desirable that it be large.

To explain the operation of the memory cell according to the operation waveforms shown in FIG.
-4V tofi &), p + + channel NO8 transistor 42 is turned on. At this time, the write line voltage Vw
becomes -IV or 1=41, respectively, according to the information "o" and "i" to be examined. p-channel MO8) If the threshold value of transistor 12 is -IV, storage capacitance C1l?
is changed to 11■ for "O'" information, and 13■ for "11 information," and the desired information is written.

When the word line voltage vA returns from ■□1 to 0■, the coupling valley tC
Due to A, the accumulated voltage of the capacitor CRT increases by vAW-CA/C8 (■), and this state is maintained.

When reading, check the aperture line RR' in advance. The edge set to ■ is in an electrically floating state, and the next #Ivl!
Voltage ■, VA, -2,OV Nit6゜n channel M
O8) The transistor 15 has a threshold value of +1v when the board 16 is written to "0", but the threshold value is +1v when the board 16 is written to 11
When it is written in , the threshold value is +2.2■. n-channel MO8) If the transistor threshold is 1V, the thread removal current is 1IRR' as read from the n-channel MOB 13.
flows, and the read line voltage becomes approximately 0°8■ On the other hand, n
If the threshold value of the channel MO8 transistor is 2.2■, it will not conduct during gun picking, and the read line voltage will remain at 0.0 Now, during gun picking, the storage capacitance C8 will be ? The potential of is further ■, 1L than the holding state.
-C,/c8T(v), the potential of the storage capacitor car during reading is (VA II+VAW)Ch/Cs ys-(-1+4
．． 5CA/C5y) (Vl, and in the 11" accumulation state, (VAll + VAN) CA/CB = (-3 + 4.50
A/CIT) becomes M.

Now, in response to the “0゛ information, the writing line static” is maintained.
Suppose that A voltage 0■ is written.O At this time, if the ratio of word line coupling capacitance C1 to storage voltage 1i Cs is 017
If this is the case, the voltage of the capacitor csy in the "θ" storage state will be 0.7 or more, and since it is set in the II type paper resistance diffusion layer 310, which is the dedication line, the pn&connection will be in the forward direction. Be biased. This 2T cell is a non-destructive ILIt
However, as mentioned above, when the pn junction in the “θ′” accumulation state is forward biased, the accumulation of “1” and “θ” due to the stripping operation reduces the compression. , the operating margin will be reduced.The present invention attempts to set the "O" information level in consideration of potential fluctuations due to such coupling capacitance.
The Oll and iJ information levels are not set to normal OV (ie, no polarity), but the "l" information level and value are different but have the same polarity. In the embodiment described in detail here, the number is 11.

The reading and b reading is from the substrate area fi13 to which the substrate voltage +2.5■ is applied, through the n-channel MO8) transistor 15, and reads the floating state set in advance to Ov!
l! This is done by detecting whether or not a current flows to B' or whether the voltage of read line RR' rises to a positive potential or remains at 0 as a result. Therefore, N
Channel MO8) Since the transistor 15 operates as a source follower, the readout current is 1iR.
When the voltage of H increases, the potential in the %pm region increases due to the read line RR and the combined capacitance C1l after the p-type wiring.

If the voltage increase of the read line is Δv1, the potential increase due to the gun collection group is ΔV to CH/CB y. Therefore, the potential of the capacitor C3T in the "0'" accumulation state is -
Even if this potential exceeds 0.7V, the potential of the surrounding pm region is also rising, so there is no need to consider that the pn junction is forward biased. However, in the half-selected memory cell connected to the selected read line RR' and connected to the unselected II line A', the potential of the capacitor CSt in the "0" storage state is IV
When the gate voltage exceeds 0 VIC, the p-channel MO8 transistor 1 for writing of the threshold value -IV is applied with 0 VIC.
2 becomes conductive, and the 10'' storage potential approaches the 1' storage potential. This phenomenon also reduces the completion of operation 11, so the writing level of 10'' information becomes negative to about -IV. It is necessary to keep it.

As mentioned above, in a 2T cell, the substrate capacitance CB% that constitutes the storage capacitance C0, the starting line coupling capacitance C□'
, and the accumulated potential of the p-type region which is in an electrically floating state due to the loose coupling capacitance CR fluctuates, so it is important to take these potential fluctuations into consideration for the write signal. This idea brings outstanding practical effects.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of the basic configuration of a 2T cell implemented using MO8 transistors. Figure 2 is an example of the same circuit constructed using a silicon gate process. FIG. Figure 93 shows the second
FIG. 4, which is a cross-sectional view taken along line AA' in the figure, is a diagram illustrating operation waveforms of various parts. In the figure, s 11% 21.31 is @; i conductivity type tlc1-
A electrode part, 12.22s32 is the gate electrode part of the first FET, 13.33 is the J21fiV substrate area, 14.2
4.34 is the second conductivity type, 11 copies [1ff1 copy, 15%
25.35ha M 2 FW'l'(2)'7' -)
IIL part, 16.26.36 is the 1st FF, 'I' copper 2 current carrying part, 2nd PET board area, AA
' indicates the candy part, RR indicates the reading line section, WW' indicates the write-in section, and CRC and C indicate the capacitance associated with each section. Base 2 Unreasonableness

Claims (1)

[Claims] A first I FIT of a first conductivity type having a gate electrode, a first current-carrying electrode, an electrically floating II2 current-carrying electrode, and a substrate region to which a reference potential is supplied; a second current-carrying electrode to which a reference potential is supplied;
and the first FET a) a second conductive second FIT having a substrate region directly connected to the second current-carrying electrode and electrically floating; a) a write line connected to the iris 1 current-carrying electrode of the first FBT for supplying a charge to the substrate region and a write signal for setting the threshold voltage of the second FIT to either a high or a low side; When the second FFl'l' is energized, the first energization 4kk is applied to the second FFl'l' so as to sense a read signal for detecting the conduction state of the second rg'r.
The reading line connected to M, and the above first F when writing.
The first FET is configured to supply a signal that turns on only the IT, and supplies a signal that can turn on at least one of the second FETs set to either the high or low threshold voltage during reading. In a semiconductor memory cell equipped with a PFiT and a lead line commonly connected to each gate electrode of the FBT, write signals corresponding to write binary information supplied to the write line have different amplitudes and the same polarity. A semiconductor memory cell characterized by certain things.