JPS5864036A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5864036A
JPS5864036A JP16392281A JP16392281A JPS5864036A JP S5864036 A JPS5864036 A JP S5864036A JP 16392281 A JP16392281 A JP 16392281A JP 16392281 A JP16392281 A JP 16392281A JP S5864036 A JPS5864036 A JP S5864036A
Authority
JP
Japan
Prior art keywords
layer
nickel
indium
thickness
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16392281A
Other languages
Japanese (ja)
Inventor
Shuzo Ito
伊藤　修三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP16392281A priority Critical patent/JPS5864036A/en
Publication of JPS5864036A publication Critical patent/JPS5864036A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To improve the soldering property which will be performed for fixing of a pellet as well as to obtain the semiconductor device having excellent adhesive strength, electric resistance and thermal resistance by a method wherein, when a heat treatment is performed after a chromium layer, a nickel layer and a silver layer have been successively formed by vapor-deposition, an indium layer is interposed between the mickel layer and the silver layer. CONSTITUTION:A plurality of semiconductor elements are formed by performing diffusion on a silicon semiconductor substrate, a processed semiconductor substrate (1) whereon an electrode was formed on the surface is prepared, and after said substrate 10 has been thinned off and activated by performing honing on the back side (2), a chromium layer of 100-1,000Angstrom or thereabouts in thickness is formed by vapor-deposition (3), a nickel layer of 1,000-10,000Angstrom or thereabout in thickness is formed on the chrome layer (4), an indium layer of 100-1,000Angstrom or thereabouts in thickness is formed on the nickel layer (5), and in addition, a silver layer of 1,000-10,000Angstrom or thereabouts in thickness is formed on the indium layer (6). Then, an alloy layer consisting of the chromium layer and the silicon semiconductor substrate is formed by performing a heat treatment (7) in a nitrogenous atmosphere at the temperature of the melting point of indium or above.

Description

【発明の詳細な説明】 この発明は半導体装置の製造方法に関し、特にオーミン
ク電極の形成□方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming an ohmink electrode.

トランジスタ、サイリスタ、ダイオード等の半導体装置
において、ペレ７・；ト裏面のオーミック電極は、この
ベレフトをステ台、リードフレーム等の素子取付基板に
マウントする場合の機械的な半田付は性や、半田付は後
のベレットと素子取付基板との間の電気抵抗や熱抵抗を
決定する重要なも・のである。In semiconductor devices such as transistors, thyristors, diodes, etc., the ohmic electrode on the back side of the plate 7. The attachment is important in determining the electrical resistance and thermal resistance between the pellet and the element mounting board.

従来は、シリコン半導体基板の裏面をホーニングして粗
面化および活性化したのち、無電解メッキで１次二・ツ
ケルメツキ朧を形成し、加熱処理してニッケルとシリコ
ンの合金層を形成し、コツケルメッキ層中のニッケルの
シリコンとの合金化によりリンの含有量が多く脆い残存
した１次ニッケルメッキ層をエツチングにより除去し、
次いテ露出Ｌｌニッケルとシリコンの合金層の上に、電
気メツキ法または無電解ノーフキ法で一次ニッケルメッ
キ編を形成し、さらにこの２次ニッケルメッキ層上に金
メッキ層を形成することによりオーミック電極を形成し
ていた。しかしながら、この方法は湿式法であるため、
薬液の保管、保ず、排液の処理といった煩雑さがあるの
みならず、無電解ニッケルメッキ層は塩化ニッケルを次
亜リン酸で還元して形成するので、本雀的に水素ガスを
吸蔵しやすく、吸蔵ガスがペレットマウント時に溶ＩＭ
半田中に出てくると泡となって、冒頭に述べた回漕強度
や電気抵抗、熱抵抗等の諸特性に悪影響を及ぼすので、
吸蔵ガスの除去に工夫を要するといった問題点があった
。Conventionally, after honing the back surface of a silicon semiconductor substrate to roughen and activate it, electroless plating is used to form a primary secondary nickel-silicon alloy layer, followed by heat treatment to form an alloy layer of nickel and silicon. The remaining primary nickel plating layer, which has a high phosphorus content and is brittle due to alloying of nickel with silicon in the layer, is removed by etching.
Next, a primary nickel plating layer is formed on the exposed Ll alloy layer of nickel and silicon by an electroplating method or an electroless no-plating method, and a gold plating layer is further formed on this secondary nickel plating layer to form an ohmic electrode. was forming. However, since this method is a wet method,
Not only is it complicated to store and maintain chemical solutions and treat wastewater, but since the electroless nickel plating layer is formed by reducing nickel chloride with hypophosphorous acid, it is difficult to absorb hydrogen gas. It is easy to dissolve IM when the absorbed gas is mounted on the pellet.
If it comes out in the solder, it will form bubbles and have a negative effect on the various properties mentioned at the beginning, such as rolling strength, electrical resistance, and thermal resistance.
There was a problem in that it required some ingenuity to remove the occluded gas.

そのため、シリコン半導体基板の裏面にクロム額、ニツ
ナル層、銀層を蒸着により順次ｂｔｋ形成したのち、加
熱処理してりＰムとシリコンの合金層を形成する方法も
提案され″ｒニーる０この方法は乾式法であるため、先
に述べた湿式法の問題点は皆無であるが、加熱処理して
クロムとシリコンの合金層を形成する場合に、開管型の
炉心管を用いて熱処理すると、特にその熱処理が終った
半導体基板を炉心管から引き出す際に、炉心管内に空気
が侵入して、この空気が比較的結晶構造の粗い銀層を通
ってニッケル層を酸化しやすかったＯもしニッケル層が
酸化きれると、ペレットマウント時に溶融半田中に銀が
食われてニッケル肱・か溶融半田と接触したとき、表面
の酸化膜のためにニッケルと半田との濡れ性が悪く、ペ
レットマウントか不可能となったり、−見マウントされ
ているかのように見えても、僅かの外力で簡単に剥離し
たり、電気抵抗や熱抵抗が非常に大きくなるという問題
点かあった。Therefore, a method has been proposed in which a chromium layer, a silver layer, and a silver layer are sequentially formed by vapor deposition on the back surface of a silicon semiconductor substrate, and then heat treated to form an alloy layer of phosphorus and silicon. Since the method is a dry method, there are no problems with the wet method mentioned above.However, when heat-treating to form an alloy layer of chromium and silicon, it is difficult to heat-treat using an open core tube. In particular, when the heat-treated semiconductor substrate is pulled out of the furnace tube, air enters the furnace tube, and this air easily oxidizes the nickel layer through the silver layer, which has a relatively coarse crystal structure. If the layer is completely oxidized, the silver will be eaten away by the molten solder during pellet mounting and when it comes into contact with the nickel or molten solder, the wettability of the nickel and solder will be poor due to the oxide film on the surface, and the pellet mount will be damaged. Even if it appears to be mounted, there are problems in that it easily peels off with a slight external force, and the electrical resistance and thermal resistance become extremely large.

それゆえ、この発明の主たる目的に、オーミック電極′
を蒸着法で簡単に形成でき、しかもクロムとシリフンの
合金層を形成する熱処理によってニッケル層が酸化され
なＶ・半導体装置の製造方法を提供することである。Therefore, the main purpose of this invention is to
It is an object of the present invention to provide a method for manufacturing a V semiconductor device which can be easily formed by a vapor deposition method and in which a nickel layer is not oxidized by heat treatment for forming an alloy layer of chromium and silicon.

この発明は要約すると、クロム脂、ニッケル層。This invention can be summarized as chromium fat and nickel layer.

銀層を蒸着により順次積層形成したのち熱処理する方法
において、前記二フィル層と銀層との間にインジウム層
を介在したことを特徴とする。A method in which silver layers are successively formed by vapor deposition and then heat treated, characterized in that an indium layer is interposed between the two-fill layer and the silver layer.

以下、この発明の実施例を図面を参照して説明する０第
１図はこの発明の製造方法の各工程のブロック図を示し
、第２図は半導体基板の要部の拡大断面図を示す。まず
、シリコン半導体基板ｌＯに拡蔽によって多数の半導体
素子を形成し、表面に電極を形成済みの処理済み半導体
基板ｌＯを用意しく第１図１）、その１面をホーニング
によって薄型化および活性化したのち（第１図２）、蒸
着により厚さが１００〜１，０ＯＯＡ程度のクロム層１
１を形成しく第１図３）、その上に厚さが１，０００〜
ｌｏ、ｏｏｏＸ稈度のニッケル層１２を形成しく第１図
４）、その上に厚さが１００〜１．Ｑ　ＯＯＡ程度のイ
ンジウム層１３を形成しく第１１Ｊ５）、式らにそ〜 の上に厚さが１，０００〜１０，０ＯＯＡ程度の銀層１
４を形成する（第１図６）Ｏこののち、窒素雰囲気中に
おいてインジウムの融点（１５６，４℃＞以上ｏｔｉ度
、　例ｊｔｌｄ　１６０〜５００℃Ｔ　１０〜６０　分
ｉｊｌ　ＪＩＪＬＩ熱処理してクロム層１１とシリコン
半導体基板ｌＯとの合金４１６を形成する（第１図７）
。上記の半導体基板を各半導体素子毎□に切断分離して
得たペレットを半田により素子取付基板にマウントした
ところ、半田付は性も良好で、従来のようなベレット剥
離や電気抵抗、熱抵抗不良に詔められなかった。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of each step of the manufacturing method of the invention, and FIG. 2 shows an enlarged cross-sectional view of the main part of a semiconductor substrate. First, a large number of semiconductor elements are formed on a silicon semiconductor substrate 10 by expansion, and a processed semiconductor substrate 10 with electrodes formed on its surface is prepared (Fig. 1), and one surface thereof is thinned and activated by honing. After that (Fig. 1, 2), a chromium layer 1 with a thickness of about 100 to 1,0 OOA is formed by vapor deposition.
1 (Fig. 1 3), with a thickness of 1,000~
A nickel layer 12 of lo, oooX culmosity is formed (FIG. 14), and a nickel layer 12 with a thickness of 100 to 1.0 mm is formed thereon. Form an indium layer 13 with a thickness of about Q OOA (No. 11J5), and then form a silver layer 1 with a thickness of about 1,000 to 10,000 OOA on top of the equation.
4 (FIG. 1 6) O After this, in a nitrogen atmosphere, the melting point of indium (156,4℃> or more degrees, e.g. 160~500℃T 10~60 minutes) is heat treated to form the chromium layer 11. and a silicon semiconductor substrate lO to form an alloy 416 (FIG. 1, 7).
. When the pellets obtained by cutting and separating the above semiconductor substrate into □ parts for each semiconductor element were mounted on an element mounting board by soldering, the soldering properties were good, and there were no pellet peeling or electrical resistance/thermal resistance defects as in the conventional method. was not admonished.

これはインジウム層１３が、加熱処理によって溶融して
銀層１４と緻密な合金層を作り、万一炉心管内に空気か
入り込んで会でも、ニッケル層か酸化することを防止し
、しかも前記合金層は後のベレットマウント時に溶融し
た半田となじみやすいためであると考えられる。This is because the indium layer 13 is melted by heat treatment to form a dense alloy layer with the silver layer 14, and even if air enters the core tube, the nickel layer is prevented from being oxidized, and the alloy layer This is thought to be because it easily blends in with the molten solder during subsequent bullet mounting.

この発明は以上のように、ニッケル層と銀層との間にイ
ンジウム麺を介在したから、熱処理時に炉心管内に空気
が侵入しても、ニンケル層か酸化されることがなくなり
、ベレットを素子取付板に固着するときの半田付は性に
優れ、固着強度、電気抵抗、熱抵抗の優れた半導体装置
か得られるという効果を奏する。As described above, in this invention, since the indium layer is interposed between the nickel layer and the silver layer, even if air enters the furnace tube during heat treatment, the nickel layer will not be oxidized, and the pellet can be attached to the element. Soldering properties when bonding to a plate are excellent, and a semiconductor device with excellent bonding strength, electrical resistance, and thermal resistance can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

ｆＰ１図はこの発明の半導体製造方法の各工程のブ′ｏ
７．図、あ２図。。。発明えよ、半導体装置。 要部拡大断面図である。 １０・・・・・半導体基板、 １１・・・・・・　クロム層、 １２・・・・・・　ニッケル層、 １３・・・・・・インジウム層、 １４・・・・・・銀層。fP1 diagram shows the blocks of each step of the semiconductor manufacturing method of this invention.
7. Figure, A2 Figure. . . Invent a semiconductor device. FIG. 3 is an enlarged cross-sectional view of main parts. 10...Semiconductor substrate, 11...Chromium layer, 12...Nickel layer, 13...Indium layer, 14...Silver layer.

Claims (1)

【特許請求の範囲】 シリコン半導体基板に蒸羞により、クロム族。 ニッケル層、インジウム層および銀層を順次積層形成し
、熱処理を施すことを特徴とする半導体装置の製造方法
。[Claims] Chromium group by vapor deposition on a silicon semiconductor substrate. A method for manufacturing a semiconductor device, comprising sequentially forming a nickel layer, an indium layer, and a silver layer, and subjecting the layers to heat treatment.
JP16392281A 1981-10-13 1981-10-13 Manufacture of semiconductor device Pending JPS5864036A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16392281A JPS5864036A (en) 1981-10-13 1981-10-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16392281A JPS5864036A (en) 1981-10-13 1981-10-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5864036A true JPS5864036A (en) 1983-04-16

Family

ID=15783367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16392281A Pending JPS5864036A (en) 1981-10-13 1981-10-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5864036A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694663A (en) * 1979-12-27 1981-07-31 Nec Home Electronics Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694663A (en) * 1979-12-27 1981-07-31 Nec Home Electronics Ltd Semiconductor device

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