JPS5863884A - Electronic clock - Google Patents

Electronic clock

Info

Publication number
JPS5863884A
JPS5863884A JP16249181A JP16249181A JPS5863884A JP S5863884 A JPS5863884 A JP S5863884A JP 16249181 A JP16249181 A JP 16249181A JP 16249181 A JP16249181 A JP 16249181A JP S5863884 A JPS5863884 A JP S5863884A
Authority
JP
Japan
Prior art keywords
circuit
voltage
battery
electronic
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16249181A
Other languages
Japanese (ja)
Inventor
Tatsuo Moriya
守屋 達雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP16249181A priority Critical patent/JPS5863884A/en
Publication of JPS5863884A publication Critical patent/JPS5863884A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G3/00Producing timing pulses
    • G04G3/02Circuits for deriving low frequency timing pulses from pulses of higher frequency
    • G04G3/022Circuits for deriving low frequency timing pulses from pulses of higher frequency the desired number of pulses per unit of time being obtained by adding to or substracting from a pulse train one or more pulses

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Electric Clocks (AREA)
  • Electromechanical Clocks (AREA)

Abstract

PURPOSE:To keep the output period of a clocking electronic circuit approximately at a fixed level even if battery voltage is changed and stabilize its accuracy by carrying out the logical changing processing in accordance with the value of power voltage. CONSTITUTION:The voltage of a power source 6 is detected by a voltage detecting circuit 5 in accordance with a sampling pulse outputted from a smapling pulse generating circuit 4 controlled at a prescribed step of divided outputs through a crystal oscillator 1, an oscillating circuit 2 and a frequency dividing circuit 3. In accordance with the detected voltage, a logical changing pulse is outputted from a logical changing pulse generating circuit 7 and inputted to a FF having a setting terminal in the circuit 3 to execute logical changing processing. Even if the voltage of the power source 6 is changed, the output period of the clocking electronic circuit controlling a clock driving circuit 8 etc., is kept approximately at a fixed level by the output of the circuit 3 and stable accuracy is kept. Consequently a lithium battery, a silver peroxide battery having a high potential division and a solar battery can be combined as a power battery, making it possible to form a long-life and small-sized electronic clock.

Description

【発明の詳細な説明】 本発明は電源電圧の変化に伴なう時用°用電子回路の発
振周波数の変化を補正する手段に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to means for correcting changes in the oscillation frequency of an everyday electronic circuit due to changes in power supply voltage.

従来の電子時計には、電源↑ぽ1圧が変化すると時計用
電子回路の発1/、硬周波数が変化するという欠点があ
った。0−MO8回路の場合は第1図に示すように、0
.1■につき約0.5〜0.7ppm変化し、これは月
差に換算するとα1■につき約1.3〜1.8秒となる
。従来電子時計の電源として用いられていた酸化錫電池
は第2図Aに示すように放電電圧が一定であるため前述
の発振周波数の変化は考慮する必要はなかったが、周知
の通り、近来の電子時計の長力命化に伴ない電源として
リチウム電池、高電位区間を有する過酸化銀電池、−次
電池として太陽電池を用いて充電する二次電池が頻繁に
用いられるようになった。しかしこれらの電源は第2図
Bから第2図Eに示すように放電電圧が変動する。第2
図BはBR系リチウム電池、第2図CはOR系リチウム
電池、第2図りは高電位区間を有する過酸化銀電池、第
2図Fは−次電池として太陽電池を用い二次電池に酸化
銀電池を用いるシステムの放電特性の一例である。それ
ぞれの電源の電圧変化及び電圧変化に伴なう発振周波数
の変化をまとめると表1の様になる。
Conventional electronic watches have had the disadvantage that when the power supply voltage changes, the oscillation 1/hard frequency of the watch electronic circuit changes. In the case of the 0-MO8 circuit, as shown in Figure 1, 0
.. It changes by about 0.5 to 0.7 ppm per 1■, which is about 1.3 to 1.8 seconds per α1■ when converted into a monthly difference. As shown in Figure 2A, tin oxide batteries conventionally used as a power source for electronic watches have a constant discharge voltage, so there was no need to take into account the aforementioned change in oscillation frequency. As electronic watches have extended their lifespans, lithium batteries, silver peroxide batteries with a high potential range, and secondary batteries that are recharged using solar cells have come to be frequently used as power sources. However, the discharge voltage of these power sources fluctuates as shown in FIG. 2B to FIG. 2E. Second
Figure B is a BR type lithium battery, Figure 2C is an OR type lithium battery, the second diagram is a silver peroxide battery with a high potential section, and Figure 2F is a secondary battery using a solar cell as a negative battery. This is an example of the discharge characteristics of a system using silver batteries. Table 1 summarizes the voltage changes of each power source and the changes in oscillation frequency due to the voltage changes.

表  1 表1の中でリチウム電池の電圧を2で割っているのは、
3V糸リチウム電池を電源として用いる時計用電子回路
では通常/2に降圧した電圧を印加していることを考慮
したものである。表1から明らかなように、これらの電
源を用いた場合月差3〜9秒の周波数変化を生じ、月差
5〜10秒の高精度時計にはこれらの電圧変ルbの大き
い電源を用いることは不可能であった。
Table 1 In Table 1, the voltage of the lithium battery is divided by 2.
This is done in consideration of the fact that in a watch electronic circuit using a 3V string lithium battery as a power source, a voltage stepped down to /2 is usually applied. As is clear from Table 1, when these power supplies are used, the frequency changes by 3 to 9 seconds per month, and for high-precision clocks with a monthly difference of 5 to 10 seconds, these power supplies with a large voltage variation b are used. That was impossible.

本発明はかかる欠点を除去したもので、その目的は電源
電圧が変動して時用用電子回路の発振周波数が変化して
も、’rrL源電n:、の値に応じて論理緩急すること
により時計用電子回路の出力周期をほぼ一定に保ち、安
定した精度をに’Jることにある。
The present invention eliminates such drawbacks, and its purpose is to adjust the logic according to the value of 'rrL power supply n:, even if the oscillation frequency of the electronic circuit for use changes due to fluctuations in power supply voltage. The aim is to keep the output period of the watch electronic circuit almost constant and achieve stable accuracy.

本発明の他の目的はリチウム電池又は高電位区間を有す
る過酸化銀電池又は−次電1池として太陽電池を用いて
充電する二次電池を電源に用い、長寿命かつ高精度の電
子時計を実現することにある以下実施例に基づいて本発
明を説明する。
Another object of the present invention is to provide a long-life and high-precision electronic clock using a lithium battery, a silver peroxide battery having a high potential range, or a secondary battery that is charged using a solar cell as a secondary battery as a power source. The present invention will be described below based on embodiments in which it is realized.

まず第3図に示すブロック図により本実施例の概略を説
明する。1は水晶振動子であり、発振回路2に接続され
32768 HZの発振をする。この信号は分周回路3
に導入されフリップフロップにより順次分周され他のブ
ロックの必要とする信号を発生する。4はサンプリング
パルス発生回路で、3で分周された信号を合成し、電圧
検出及び論理緩急のタイミングを作りだす。5は電圧検
出回路で前述のサンプリングパルスが入力した時に電源
乙の電圧を検出する。7は論理緩急用パルス発生回路で
、サンプリングパルス発生回路4と電圧検出回路の出力
を合成し、電源電圧に応じて何種類かの論理緩急用パル
スを発生する。この論理緩急用パルスを分周回路3の中
のセット端子付フリップフロップに導入して論理緩急す
ることにより駆動回路8には安定した周期の出力が導入
される。
First, the outline of this embodiment will be explained with reference to the block diagram shown in FIG. Reference numeral 1 denotes a crystal resonator, which is connected to the oscillation circuit 2 and oscillates at 32768 Hz. This signal is the frequency divider circuit 3
The signals are introduced into the blocks and sequentially divided by flip-flops to generate signals required by other blocks. 4 is a sampling pulse generation circuit, which synthesizes the signals frequency-divided by 3 and generates voltage detection and logic slow/fast timing. 5 is a voltage detection circuit which detects the voltage of the power supply B when the above-mentioned sampling pulse is input. Reference numeral 7 denotes a logic regulation pulse generation circuit which combines the outputs of the sampling pulse generation circuit 4 and the voltage detection circuit and generates several types of logic regulation pulses depending on the power supply voltage. By introducing this logical adjustment pulse into a flip-flop with a set terminal in the frequency dividing circuit 3 to perform logical adjustment, an output with a stable period is introduced to the drive circuit 8.

次に各ブロックの詳細図及びタイミングチャートにより
本発明の詳細な説明する。
Next, the present invention will be explained in detail with reference to detailed diagrams and timing charts of each block.

第4図Aは本実施例に用いた発振回路2I分周回g3+
サンプリングパルス発生回路4の接続図であり、第4図
Bはそのタイミングチャートである。第4図Aにおいて
1は水晶振動子、2は発振回路、9,10,11,12
.13はクロック(以後OLと書く)が立ち下がるとき
出力Qが変化し、OLが立ち上がるとき出力Q、Mが変
化するマスタースレーブ型フリップフロップである。尚
、フリップフロップ10には” H”のときθが”H”
、■がL#になるセット端子Sを具備している。14.
15はOLが@ 1,1 #でデータを通過、OLが”
L”でデータをホールドするラッチ回路である。端子o
c1には100秒カウンタと512Hzの信号を合成す
ることにより得られるパルス幅9.81nsecの微分
信号が加えられる。発振回路2は水晶振動子1を源振と
して327(S8H2の基準信号を発生する。この基準
信号はフリップフロップ9,10,11,12.15に
より順次分周され、Sl  eS!  wall  *
S4  mSs  lS6*S’r、S、の信号をつく
りだす。サンプリングパルス発生回路4では、信号”B
+”+1をラッチ回路14に、信号”5sS11をラッ
チ回路15に導入して信号SOs”1Gをつくり、xl
  e S11  e ”I  tSII+S9t”1
0の信号をゲート16,17.18゜19.20,21
,22.23で合成して4相のサンプリングパルスz1
.ZI 、z3 、z4を又、サンプリングパルスz1
  * zt  # z3 1 Z4をORゲート24
で合成して信号z0をつくりだす第6図Aは電圧検出回
路5、電源25、論理緩急用パルス発生回路7の接続図
である。25は電池の回路電圧VDを発生する理想電池
で、端子VD、Vsは工Cの端子である。図において電
池25以外はすべて工0に内蔵されている。
Figure 4A shows the oscillation circuit 2I frequency division g3+ used in this example.
It is a connection diagram of the sampling pulse generation circuit 4, and FIG. 4B is its timing chart. In Fig. 4A, 1 is a crystal resonator, 2 is an oscillation circuit, 9, 10, 11, 12
.. 13 is a master-slave type flip-flop whose output Q changes when the clock (hereinafter referred to as OL) falls, and whose outputs Q and M change when OL rises. Furthermore, when the flip-flop 10 is "H", θ is "H".
, ■ is provided with a set terminal S that becomes L#. 14.
15, OL passes the data @ 1, 1 #, OL "
It is a latch circuit that holds data at “L”.Terminal o
A differential signal with a pulse width of 9.81 nsec obtained by combining a 100 second counter and a 512 Hz signal is added to c1. The oscillation circuit 2 generates a reference signal of 327 (S8H2) using the crystal oscillator 1 as a source oscillation. This reference signal is sequentially frequency-divided by flip-flops 9, 10, 11, 12.
S4 mSs lS6*S'r, S, generates a signal. In the sampling pulse generation circuit 4, the signal "B"
+"+1 is introduced into the latch circuit 14 and the signal "5sS11 is introduced into the latch circuit 15 to create the signal SOs"1G, xl
e S11 e “I tSII+S9t”1
0 signal to gates 16, 17.18° 19.20, 21
, 22.23 are synthesized to produce a four-phase sampling pulse z1
.. ZI, z3, z4 and sampling pulse z1
* zt # z3 1 OR gate 24 for Z4
FIG. 6A is a connection diagram of the voltage detection circuit 5, the power supply 25, and the logic pulse generation circuit 7. 25 is an ideal battery that generates a battery circuit voltage VD, and terminals VD and Vs are terminals of the circuit C. In the figure, everything except the battery 25 is built into the unit 0.

電圧検出回路はコンパレータ26と基準電圧発生部27
と、電源の分圧部28の3ブロツクからなっている。コ
ンパレータ26は入カニ+とニーの電圧の高低を比較し
て、工+〉ニーのとき出力が”H”となる。インバータ
29はコンパレータのバッファであると同時にコンパレ
ータ出力を反転させる。V comp  はインバータ
29の出力である。コンパレータは一般に作動時に電力
を消費するので、z0信号が′H#のときだけNMO8
FKT30がONしコンパレータ26は動作する。
The voltage detection circuit includes a comparator 26 and a reference voltage generator 27
It consists of three blocks: and a voltage dividing section 28 of the power supply. The comparator 26 compares the voltage levels of the input crab + and knee, and when the input voltage is higher than knee, the output becomes "H". Inverter 29 serves as a buffer for the comparator and at the same time inverts the comparator output. V comp is the output of inverter 29. Since the comparator generally consumes power when operating, NMO8 is activated only when the z0 signal is 'H#.
The FKT 30 turns on and the comparator 26 operates.

基準電圧発生部27は等価的に電圧v0の電池と考えら
れる。この基準電圧発生のためにも電力を消費するので
スイッチ31が等価的に入り2゜信号が” H”のとき
だけ動作する。基準電圧発生部27の一例を第5図Bに
示す。HMO8?ICT37はスレッシ−a kド電圧
VTIII又、NMO5FFliT36はスレッショル
ド電圧VTII2となる様、イオンの打込みによりコン
トロールされている。
The reference voltage generating section 27 can be equivalently considered as a battery with a voltage v0. Since power is consumed to generate this reference voltage, the switch 31 is equivalently turned on and operates only when the 2° signal is "H". An example of the reference voltage generating section 27 is shown in FIG. 5B. HMO8? The ICT37 is controlled to have a threshold voltage VTIII, and the NMO5FFliT36 is controlled by ion implantation to be a threshold voltage VTII2.

こうすると出力■。は V(1=VTH1−VTII2 となる。NMO8TIF!T37のゲートにコントロー
ル信号2゜を印加する事ににリスインチ31の動作が可
能となる。
This will output ■. is V(1=VTH1-VTII2).The operation of the reset inch 31 becomes possible by applying a control signal of 2 degrees to the gate of NMO8TIF!T37.

次に電源の電圧部28の動作を説明する。もし端子z1
が1H”となるとNIJOEIF11nT32がONし
、N M OS、 ? Ei T 32のON抵抗=0
とすると ■M=v1@R1(Ro  −1−R,)となり、この
VMがコンパレータ26の工+端子に入力され、voと
比較される。今、駆動電圧Vnが変化した場合検出すべ
き電圧をVnt  t”ts■Dm+■D4 とすると
以下の式からR6,R19R19RR#R4の比を決め
ることができる。
Next, the operation of the voltage section 28 of the power supply will be explained. If terminal z1
When becomes 1H”, NIJOEIF11nT32 turns ON, and ON resistance of NMOS, ? Ei T32 = 0
Then, ■M=v1@R1(Ro-1-R,), and this VM is input to the + terminal of the comparator 26 and compared with vo. Now, if the voltage to be detected when the drive voltage Vn changes is Vnt t''ts■Dm+■D4, then the ratio of R6, R19R19RR#R4 can be determined from the following equation.

vn、 =(1+Ro /Rs )v。vn, = (1+Ro/Rs)v.

VDv =(1+Ro / (Rs +R2) )V。VDv=(1+Ro/(Rs+R2))V.

Va、 =(1+Ro/ (J +J +Rs ) )
V。
Va, =(1+Ro/(J+J+Rs))
V.

VD4−(1+Ro /(Rt + Rz +Rs +
 R4) )V。
VD4-(1+Ro/(Rt+Rz+Rs+
R4))V.

これらの式において■。は一定の値であり、各式の抵抗
の比は工0上のパターンの長さ比で設定できるため各式
のynの値は正確に設定できる。以上の様に設定した状
態で端子zo 、zl lz2 。
■ In these formulas. is a constant value, and the ratio of the resistances in each equation can be set by the length ratio of the pattern on the surface, so the value of yn in each equation can be set accurately. With the above settings, connect the terminals zo and zl lz2.

zSoz4に第4 (] EのzOw”1  rz2 
ezBrz4信号を導入し、V oomp  とz。を
ANDゲー)38で合成すると、ANDゲート38の出
力端子Tでは第5図Cに示すいずれかの信号が得られる
。第5図CにおいてT1はVD>vDlのとき、T2は
’VD、>’VD>VD、のとき、T、はV D2 ”
:)V D>’V o、 LDとき、T、はVD、>V
D>VD4(7)とき、T、はVD4>VDのとき端子
Tに発生する信号である。
zSoz4 to 4th (] E's zOw"1 rz2
Introducing the ezBrz4 signal, V oomp and z. When the signals are combined by an AND gate 38, one of the signals shown in FIG. 5C is obtained at the output terminal T of the AND gate 38. In FIG. 5C, when T1 is VD>vDl, T2 is 'VD;when>'VD>VD, T is V D2''
:) V D>'V o, When LD, T is VD,>V
When D>VD4(7), T is a signal generated at terminal T when VD4>VD.

端子Tを第4図Aのフリップフロップ10のセット端子
に導入すれば、100秒に1回第5図CのT1〜T、の
いずれかの(t4号・がフリップフロップ10のセット
端子に入力され VD>VD、のとき□x−!−= o ppm1658
4   100 V nl)V D>V D、のとき 16684 ×〒
00=0.6ppm’V DりV D>V D、のとき
 16384 ×100 = ”2p””1 VD3>VD>VD4のとき 1631J4 ×100
 ” ”8pp”VD4>VD  のとき   □X 
−’−= 2.4ppm16384   100 出力周期が進むことになる。この様子をN示すると第6
図の39になる。VD、からVD、までをr:1.1v
違いで設定すれば、Cj−MO8発振器の電源電圧−周
波数特性40は第6因の41の様に補正され、電源電圧
の変動を±0.05 Vにおさえたことと同等である。
If the terminal T is introduced into the set terminal of the flip-flop 10 in FIG. 4A, one of T1 to T in FIG. When VD>VD, □x-!-= o ppm1658
4 100 V nl) When V D>V D, 16684 ×〒
00=0.6ppm'V D When D>V D, 16384 x 100 = "2p""1 When VD3>VD>VD4 1631J4 x 100
” “8pp” When VD4>VD □X
-'-=2.4ppm16384 100 The output cycle advances. If this situation is shown by N, the sixth
It becomes 39 in the figure. From VD to VD, r: 1.1v
If the difference is set, the power supply voltage-frequency characteristic 40 of the Cj-MO8 oscillator is corrected as in the sixth factor 41, which is equivalent to suppressing the fluctuation of the power supply voltage to ±0.05 V.

本発明は、電源電圧が変動しても、時計用電子回路の出
力周期をほぼ一定に保つことができるというすぐれた効
果を有するものである。このため従来高精度時計には用
いることのできなかったりチウム電池、高電位区間を有
する過酸化銀電池。
The present invention has the excellent effect of being able to keep the output cycle of the timepiece electronic circuit substantially constant even if the power supply voltage fluctuates. For this reason, lithium batteries and silver peroxide batteries with a high potential range could not be used in conventional high-precision clocks.

−次電池として太陽電池を用いて充電する二次電池を高
精度時計に用いることができ、その結果として、高精度
かつ長が命の電子時計の実現が可能になる。また前述の
各電源は従来用いられている酸化銀電池に比較してエネ
ルギー密度が高く、電源部を薄型、小型化することがで
き、その結果として小型、薄型のムーブメントにするこ
とが可能となり、デザイン的にすぐれた電子時計が得ら
れる。
- A secondary battery that is charged using a solar cell as a secondary battery can be used in a high-precision timepiece, and as a result, it becomes possible to realize a highly accurate and long-lasting electronic timepiece. In addition, each of the power sources mentioned above has a higher energy density than the conventionally used silver oxide batteries, making it possible to make the power supply section thinner and smaller.As a result, it is possible to create a smaller and thinner movement. An electronic clock with excellent design can be obtained.

ここまで述べてきた実施例は本発明の実施例としてはほ
んの一例にすぎず、信号X8の周期を変えること、又は
電圧検出レベルの設定を変えること、又は分周口の7リ
ツプフロツプ9,11゜12.13にもフリップフロッ
プ10と同様のセット端子を設は端子Tを導入すること
等により個々の時計用電子回路に最適の論理綬急値を設
定できる。又、電源の分圧部28の段数を増すことによ
りさらにきめの細かい補正が可能である。
The embodiments described so far are just examples of the present invention, and it is possible to change the period of the signal .13 is also provided with a set terminal similar to that of the flip-flop 10, and by introducing a terminal T, etc., it is possible to set the optimum logical peak value for each electronic circuit for a watch. Further, by increasing the number of stages of the voltage dividing section 28 of the power supply, more fine-grained correction is possible.

第1図は0−MO8発振器の電源電圧−発振周波数特性
の一例である。
FIG. 1 is an example of the power supply voltage-oscillation frequency characteristic of the 0-MO8 oscillator.

第2図は各種電源の放電特性の一例であり、Aは酸化銀
電池、BはBR系リチウム電池、0はOR系リチウム電
池、Dは高電位区間を有する過酸化銀電池、Eは一次電
池として太陽電池を用い二次電池として酸化銀電池を用
いるシステムである第3図は実施例のブロック図である
Figure 2 shows an example of the discharge characteristics of various power sources, where A is a silver oxide battery, B is a BR lithium battery, 0 is an OR lithium battery, D is a silver peroxide battery with a high potential section, and E is a primary battery. FIG. 3 is a block diagram of an embodiment of a system using a solar cell as the battery and a silver oxide battery as the secondary battery.

第4図Aは実施例の発振回路、分周回路、サンプリング
パルス発生1’ijl路の構成例であり第4図Bはその
タイミングチャートである。
FIG. 4A shows a configuration example of the oscillation circuit, frequency dividing circuit, and sampling pulse generation 1'ijl path of the embodiment, and FIG. 4B is a timing chart thereof.

第5図Aは実施例の電圧検出+i”1回路、論理緩急用
パルス発生回路の構成例である。@ 51ffl Bは
基準電圧発生部の構成例である。第5図Cは実施例の各
種論理緩急用パルスのタイミングチャートである。
Fig. 5A shows an example of the configuration of the voltage detection +i''1 circuit and the logic pulse generation circuit of the embodiment. @ 51ffl B shows an example of the structure of the reference voltage generation section. Fig. 5C shows various types of the embodiment. It is a timing chart of the logical adjustment pulse.

第6図は実施例により補正された電源電圧−周波数特性
である。
FIG. 6 shows power supply voltage-frequency characteristics corrected according to the embodiment.

1・・・・・・水晶振動子 2・・・・・・発振回路 3・・・・・・分周回路 4・・・・・・サンプリングパルス発生回路5・・・・
・・電圧検出回路 6・・・・・・電源 7・・・・・・論理緩急用パルス発生回路8・・・・・
・駆動回路 9〜13・・・・・・フリップフロップ14.15・・
・・・・ラッチ回路 16〜19・・・・・・NORゲート 20−、−23・・・・・・ANDゲート24・・・・
・・ORゲート 25・・・・・・理想電池 26・・・・・・コンパレータ 27・・・・・・基準電圧発生部 28・・・・・・電源の分圧部 29・・・・・・インバータ 30・旧・・NMO8IFET 31・・・・・・スイッチ 32〜37・・1・・NMO3FIIT38・・・・・
・ANDゲート 以  上 出願人 株式会礼睡訪精工舎 代理人 弁理士 最上  務 (A)ミ))浮 (ハ)“Jコシ1シ)各
1... Crystal resonator 2... Oscillation circuit 3... Frequency divider circuit 4... Sampling pulse generation circuit 5...
... Voltage detection circuit 6 ... Power supply 7 ... Logical adjustment pulse generation circuit 8 ...
・Drive circuits 9 to 13...Flip-flops 14.15...
...Latch circuits 16 to 19...NOR gates 20-, -23...AND gate 24...
...OR gate 25 ...Ideal battery 26 ...Comparator 27 ...Reference voltage generation section 28 ...Power supply voltage dividing section 29 ...・Inverter 30・Old・・NMO8IFET 31・・Switch 32 to 37・・1・・NMO3FIIT38・・・
・AND gate and above Applicant Rei Suiha Seikosha Co., Ltd. Agent Patent Attorney Tsutomu Mogami

Claims (3)

【特許請求の範囲】[Claims] (1)少なくとも電源及び時計用電子回路から構成され
る電子時計において、前記時計用電子回路内に前記電源
の電圧検出回路と論理緩急回路を設け、前記電圧検出回
路の出力に応じて前記論理緩急回路を作動させることを
特徴とする電子時計。
(1) In an electronic timepiece comprising at least a power supply and a timepiece electronic circuit, a voltage detection circuit for the power supply and a logic regulation circuit are provided in the timepiece electronic circuit, and the logic regulation regulation circuit is configured to adjust the logic regulation according to the output of the voltage detection circuit. An electronic clock characterized by operating a circuit.
(2)電圧検出回路は段階的に電源電圧を検出すること
ができ、前記電源電圧の値に応じて論理緩急回路の作動
を制御することを特徴とする特許請求の範囲第1項記載
の電子時計。
(2) The electronic device according to claim 1, characterized in that the voltage detection circuit is capable of detecting the power supply voltage stepwise and controls the operation of the logical adjustment circuit according to the value of the power supply voltage. clock.
(3)電源がリチウム電池又は高電位区間を有する過酸
化銀電池又は−次電池として太@電池を用いて充電する
二次電池であることを特徴とする特許請求の範囲第1項
及び第2項記載の電子時計。
(3) Claims 1 and 2, characterized in that the power source is a lithium battery, a silver peroxide battery having a high potential section, or a secondary battery that is charged using a thick @ battery as a negative battery. Electronic clock as described in section.
JP16249181A 1981-10-12 1981-10-12 Electronic clock Pending JPS5863884A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16249181A JPS5863884A (en) 1981-10-12 1981-10-12 Electronic clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16249181A JPS5863884A (en) 1981-10-12 1981-10-12 Electronic clock

Publications (1)

Publication Number Publication Date
JPS5863884A true JPS5863884A (en) 1983-04-15

Family

ID=15755622

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16249181A Pending JPS5863884A (en) 1981-10-12 1981-10-12 Electronic clock

Country Status (1)

Country Link
JP (1) JPS5863884A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52149464A (en) * 1976-06-08 1977-12-12 Seiko Instr & Electronics Ltd Power supply voltag e compensation oscillating circuit for electronic watches
JPS533863A (en) * 1976-06-30 1978-01-13 Seiko Instr & Electronics Ltd Electronic watch

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52149464A (en) * 1976-06-08 1977-12-12 Seiko Instr & Electronics Ltd Power supply voltag e compensation oscillating circuit for electronic watches
JPS533863A (en) * 1976-06-30 1978-01-13 Seiko Instr & Electronics Ltd Electronic watch

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