JPS5859256U - switch driver receiver circuit - Google Patents
switch driver receiver circuitInfo
- Publication number
- JPS5859256U JPS5859256U JP12519382U JP12519382U JPS5859256U JP S5859256 U JPS5859256 U JP S5859256U JP 12519382 U JP12519382 U JP 12519382U JP 12519382 U JP12519382 U JP 12519382U JP S5859256 U JPS5859256 U JP S5859256U
- Authority
- JP
- Japan
- Prior art keywords
- switch driver
- switch
- receiver circuit
- driver receiver
- branched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図および第２図は従来例の説明図、第３図′は本考
案の実施例の構成を示す説明図であり、図中１６．１６
’はラッチ回路のＮＡＮＤ回路、１７はラッチ回路出力
端、２０．２０’は伝送線、２１′はスイッチ、２２は
スイッチドライバ部、２３．２３’はダイオード、２４
． ２６． ２６’。
２７．２−ブ′は抵抗を示す。1 and 2 are explanatory diagrams of a conventional example, and FIG. 3' is an explanatory diagram showing the configuration of an embodiment of the present invention.
' is the NAND circuit of the latch circuit, 17 is the latch circuit output terminal, 20.20' is the transmission line, 21' is the switch, 22 is the switch driver section, 23.23' is the diode, 24
．． 26. 26'. 27.2-B' indicates resistance.
Claims (1)
に該２伝送線のそれぞれを別個に入力するチャタリング
吸収用ラッチ回路を設けたスイッチ信号伝送系において
、前記スイッチドライバ部に、 おけるいずれか一
方の伝送線側に抵抗を介した給電回路を分岐して設ける
とともに、前記受信側ラッチ回路の２人力部にそれぞれ
分圧抵抗を介した給電回路を分岐して設け、該ラッチ回
路の、２人力がスイッチ動作時の異常状態において異な
る論理レベルとなるように設定したことを特徴とするス
イッチドライバレシーバ回路。In a switch signal transmission system in which a switch driver section is provided on the transmitting side of two transmission lines, and a chattering absorbing latch circuit is provided on the receiving side for inputting each of the two transmission lines separately, either of the switch driver sections in the switch driver section is provided. A power supply circuit via a resistor is branched to one transmission line side, and a power supply circuit via a voltage dividing resistor is branched to each of the two power sections of the receiving side latch circuit. A switch driver receiver circuit characterized in that the switch driver receiver circuit is set to have different logic levels in an abnormal state when the switch is operated by human power.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12519382U JPS5926684Y2 (en) | 1982-08-19 | 1982-08-19 | switch driver receiver circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12519382U JPS5926684Y2 (en) | 1982-08-19 | 1982-08-19 | switch driver receiver circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5859256U true JPS5859256U (en) | 1983-04-21 |
| JPS5926684Y2 JPS5926684Y2 (en) | 1984-08-02 |
Family
ID=29919038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12519382U Expired JPS5926684Y2 (en) | 1982-08-19 | 1982-08-19 | switch driver receiver circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5926684Y2 (en) |
-
1982
- 1982-08-19 JP JP12519382U patent/JPS5926684Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5926684Y2 (en) | 1984-08-02 |
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