JPS5858813B2 - Charge transfer type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge transport type semiconductor device, and particularly to an improvement in its structure for high-density integration.

This type of device is most commonly used as a charge transfer type shift register that delays digital information by the required time and has a storage function, and as will be described later, the present invention can be applied to multiple channels to be even more effective. Since it is conspicuous, a multi-channel charge transfer shift register will be explained below as an example.

Fig. 1 is a plan view showing an example of a conventional 4-channel charge transfer type shift register, and Fig. 2 a and b are respectively Fig. 1 II.
FIG. 3 is a cross-sectional view taken along line A-IIA and line IIB-IIB.

In the figure, 1 is an active region of a p-type semiconductor substrate, 2 is an inactive region, and 3 is a meter-shaped input diffusion region 4, 5, 6, and 7 that receives information signal input and supplies signal charges accordingly.
a to 7d are transfer electrodes 8 and 7d for transferring signal charges, respectively;
9. Reference numerals 10 and 11 are first, second, third and fourth channels to which charges injected from the input diffusion region 3 are transferred, respectively; 12 is a gate insulating film formed on the active region 1; Each of the transfer electrodes 4 to 7 is formed on the active region 1 with the gate insulating film 12 interposed therebetween.

A protective insulating film 13 is formed on the upper surface of the semiconductor substrate to cover the transfer electrodes 4 to 7.

Note that the plan view of FIG. 1 is drawn ignoring the protective insulating film 13.

The operation of the 4-channel charge transfer type shift register configured as described above includes charge injection from the input diffusion region 3, charge transfer by the transfer electrodes 4 to 7, and charge detection at the output terminal (not shown). It can be divided into three stages.

FIG. 3 is a waveform diagram of each pulse necessary for this drive, and shows the transfer electrodes 4, 5, 6.7b.

7a+7b, 7c, . . . sequentially receive four-phase positive transfer pulses φ3. φb, φ.

, φd are respectively applied, and the input diffusion region 3 is supplied with an information signal input.

To explain the first channel 8, the information power p to the input diffusion region 3 is low (
Charge is injected by setting it to V level, and if the information power is at a high level during this period THa, charge is not injected.

On the other hand, during the period when the transfer pulse φ8 applied to the transfer electrode 4 is at a low level, charge is not injected into the input diffusion region 3 regardless of the information input.

The injected charges are sequentially transferred to four-phase transfer pulses φ8. The transfer operation is so-called four-phase driven by φbIφcIφd, but since this transfer operation is well known, detailed explanation will be omitted.

The operations of the second, third and fourth channels 9, 10 and 11 are similar to the operation of the first channel, except that the first transfer electrode is connected to the transfer pulse φb in the second channel 9.
, and in the third channel 10 a transport pulse φ.

In the fourth channel 11, the transfer electrode 7d is supplied with the transfer pulse φd.

Since the four-channel charge transfer type shift register has the above-described configuration, a series of information input signals can be distributed and inputted to each channel sequentially in a time-division manner, which is very efficient.

That is, the pitch value (t) when the transfer pulse φ8 of the 4-bit information input signal during one cycle T in FIG. 3 is at a high level.
t 1// ) goes to the first channel, the bit value (// Q// ) when the transfer pulse φb is at high level goes to the second channel, and the next bit value (// l// ) goes to the second channel. To the third channel, the next bit value (〃0〃) goes into the fourth channel.

In this way, high-speed, manual processing of information is possible.

However, in such a multi-channel charge transfer type shift register, as can be seen from the drawings and the above description, the area efficiency of the arrangement of the transfer electrodes is slightly reduced, which is difficult to achieve in terms of high-density integration. There are restrictions.

Therefore, a structure as shown in FIG. 4 is used to obtain a multi-channel charge transfer type shift register with an even larger number of channels.

FIG. 4a shows a top view of the same, and a sectional view taken along the line IVB--IVB.

That is, a plurality of the same patterns as shown in FIG. 1 are formed in one semiconductor chip, and transfer electrodes 4, 4', . . . ... between, transfer electrodes 5, 5
By electrically connecting between ′... and 6.6′..., information can be input in addition to the first to fourth channels 8 to 11 by manual input. The fifth to eighth channels 16 to 19 by D' are obtained.

However, for this purpose, a contact hole 14 is provided in the thick protective insulating film 13, and a connection is made through the contact hole 14 with a conductor film 15.

This conventional structure is extremely difficult to work with, and the complexity of the work increases as the degree of pattern integration increases.

The present invention has been made in view of the above points, and an object of the present invention is to provide a multi-channel charge transport type semiconductor device that does not require special manufacturing methods even when the number of channels is increased, and therefore enables high-density integration. The purpose is to

FIG. 5 is a plan view showing one embodiment of the present invention, and FIG.
6 is a surface potential curve diagram for explaining the operation of this part, FIG. 7a is a sectional view taken along the line IV-IV of FIG. This is a surface potential curve diagram for explaining the operation of this part.

In this embodiment, as shown, the first input gate electrode 20
The second input gate electrode 21 is configured as a lower layer gate electrode embedded in the gate insulating film 12, and the transfer electrodes 78 to 1d are configured as upper layer gate electrodes on the gate insulating film 12. There is.

The first input gate electrode 20 is located between the first transfer electrode 7a and the input diffusion region 3 for the first channel 8, and the first input gate electrode 20 is located between the first transfer electrode 7a and the input diffusion region 3 for the second channel 9.
, extending between the second transfer electrodes 7a and 7b;
For the channel 10, it extends between the second and third transfer electrodes 7b and the IC, and for the fourth channel 11, it extends between the third and fourth transfer electrodes IC and 7d. ing.

The second input gate electrode 21 is also connected to all successive transfer electrodes 7a t 7b + 7 for the first channel 8.
c t 7d +... for the second channel 9, not between the first and second transfer electrodes 7a and 7b, but for the third channel For the fourth channel 11, there is no gap between the second and third transfer electrodes 7b and 70, and even more so between the third and fourth transfer electrodes 7c and 7d. It is structured so that there is no in-between.

FIG. 8 is a diagram of pulse waveforms at various parts for driving this embodiment device, in which the transfer pulse φ8. φb, φ.

. φd and information signal input are the same as in the conventional device shown in FIG.

The first input gate 20 receives a gate signal pulse φ for transferring the signal charge to the input diffusion region 3 or below the transfer electrode 7a, 7b, 7c or 7.

is applied, and a DC voltage E (about 3 to 5 volts), which is several volts higher than the minimum voltage (threshold voltage) required to form a channel under the gate electrode, is applied to the second input gate 21. be done.

Each time t1. shown in FIG. t2. The surface potential curves of the first channel 8 and the second channel 9 at t3 and t4 are shown in Figures 6 and 7, respectively.
This figure corresponds to the cross-sectional position of the cross-sectional view shown in FIG.

At time t1, the information input signal is at a low level, and in the first channel 8, the first input gate 20 and the first transfer electrode 7a are at a high level, so that the charge is transferred to the input gate 20 and the first transfer electrode 7a. is injected under the transfer electrode 7a.

In the second channel 9 charge is injected under the first input gate 20 .

Next, at time t2, the first input gate 20 becomes low level, so in the first channel 8, the injected charge is accumulated under the first transfer electrode 7a, but in the second channel 9, the injected charge is accumulated under the input diffusion region 3. be sent back to

At time t3, the second transfer electrode 7b becomes high level, and the surface potential under the second transfer electrode 7b becomes deep.

Then, at time t4 when the first transfer electrode 7a becomes a low level, a DC voltage higher than the threshold voltage is applied to the second gate 21 in the first channel 8, and the second gate 2
Since a channel is formed under the first transfer electrode 7a, the charges accumulated under the first transfer electrode 7a are transferred to the second transfer electrode 7b.

As explained above, the charge injection into the first channel 8 causes the information input signal to become 1 while the transfer pulse φ8 is at a high level, including the period when the gate signal pulse φ7 exists. This is achieved by

Similarly, the second channel 9, the third channel 10, the fourth channel
The charge injection into the channel 11 is carried out by a transfer pulse φ
It will be easy to understand that this is possible while φcIφd is at a high level.

In this way, this device also operates as a 4-channel charge transfer type shift register that can time-divisionally distribute and store 4-bit input information to each channel 8 to 11 during one period T of transfer pulses.

Now, looking at this device in terms of the planar pattern shown in FIG. 5, the transfer electrodes 7a to 7d, the first input gate 20,
Since both the input gate 21 and the second input gate 21 have a portion extending over the first to fourth channels 8 to 11, a multi-channel charge transfer type shift register with a larger number of channels is constructed, as shown in FIG. 4 for the conventional example. There is no need for bridging wiring as in the conventional example, and therefore there is no need for troublesome work such as creating contact holes. Since it is only necessary to electrically connect the second input gate and the second input gate, large-capacity and high-density integration is possible without requiring any extra steps.

Furthermore, the degree of freedom of the integrated 0 pattern is large. In the above embodiment, a four-channel four-phase drive charge transfer type shift register is described, but the number of channels and drive type are not limited to this. Needless to say, the present invention can also be applied to general charge transfer type semiconductor devices such as type shift registers.

As described in detail above, in the present invention, since the unit multi-channel charge transfer type semiconductor device is configured to have the first and second input gate electrodes, each input gate electrode and each transfer electrode are completely This makes it extremely easy to connect multiple unit multi-channel charge transfer semiconductor devices when configuring a multi-channel charge transfer semiconductor device with a large number of channels. Since no extra steps are required, large-capacity, high-density integration is possible, and the degree of freedom in patterning during integration is also increased.

[Brief explanation of drawings]

Fig. 1 is a plan view showing an example of a conventional 4-channel charge transfer type shift register, and Fig. 2 a and b are respectively Fig. 1 II.
A cross-sectional view taken along the A-HA line and the IIB-IIB line, Fig. 3 is a waveform diagram of each pulse necessary for driving, and Fig. 4 shows a multi-channel charge transfer type shift using this conventional device with a larger number of channels. An example of the connection part when configuring a register is shown.
It is a sectional view at B@. FIG. 5 is a plan view showing one embodiment of the present invention, FIG. 6a is a sectional view taken along line VI-IV, FIG. Figure a is a sectional view taken along the line ■-■ in Figure 5, Figure 7 is a surface potential curve diagram for explaining the operation of this part, and Figure 8 is a pulse waveform of various parts for driving this embodiment device. It is a diagram. In the figure, 1 is an active region of the semiconductor substrate, 2 is an inactive region, 3 is an input diffusion region, 4, 5.6° γa, 7b, 7c
, 7d are transfer electrodes, 8, 9, 10° 11 and 16.1
7. 'f8.19 is the channel, 12 is the gate insulating film, 2
0 is a first input gate electrode, and 21 is a second input gate electrode. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1 a semiconductor substrate provided with a plurality of channel regions having a first conductivity type and separated from each other via an inactive region;
an input diffusion region having a second conductivity type and provided at one end of the semiconductor substrate in common to each of the channels and supplying signal charges corresponding to the information input signal; an insulating film on the semiconductor substrate in the channel region; a transfer electrode for charge transfer provided in common with the plurality of channels and arranged in a direction along the channel; a transfer electrode provided on the semiconductor substrate in the channel region with an insulating film interposed therebetween; In the nth (n is a positive integer of 1 or more) channel, the first to nth transfer electrodes are disposed insulated from each other in a portion between the input diffusion region and the nth transfer electrode.
- a first input gate electrode formed integrally so as to pass under and spread under the first transfer electrode, and a portion between the adjacent transfer electrodes on the semiconductor substrate with an insulating film interposed therebetween; a first channel region between the n-th phase shift electrode and the n+1-th transfer electrode; A charge transport type semiconductor device comprising a second input gate electrode integrally configured to extend over the n-th channel region.