JPS5858448A - Defect detecting circuit - Google Patents

Abstract

PURPOSE:To suppress the variance of a threshold to detect defects accurately, by obtaining data, which follows up a texture level, from the image pickup signal of a face to be examined of a sheet material or the like by an up/down counter and inhibiting the counting during the blank period and the defect detection period. CONSTITUTION:An image pickup element 5 consisting of a CCD sensor or the like is controlled by a driving circuit 12 to scan optically the surface of an object to be examined repeatedly. A video signal VS which is outputted from the element 5 and is amplified by an amplifier 6 is compared with a threshold signal SH, which is obtained from an amplifier 15, in level by a defect discriminating comparator 16, and a binary discrimination output OUT is outputted. The output of an up/down counter 11 is given to a D/A converter 14, and the counter 11 is counted up for VS>b and is counted down for VS<b in accorddance with an output signal (c) of a comparator 7 by the output signal (b) of the converter 14, and the operation of the counter 11 is inhibited in the blank time between scannings of the element 5 and in the time when a defect is detected by the comparator 16. The signal (b) is amplified in the amplifier 15 to obtain the signal SH.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a defect detection circuit that detects defects by photoelectrically scanning a surface to be inspected of a sheet or the like using an imaging means.

For example, as shown in FIG. 1, a sheet-like object to be inspected 3 such as paper or film is placed between an imaging device 1 and a light source 2, and the object to be inspected 3 is scanned using transmitted light. When detecting such defects, the following signal processing is basically performed.

When the I#I image device 1 is constructed using a semiconductor image sensor such as a CCD (charge coupled device), its video signal is output in the form of a high frequency pulse as illustrated in FIG. This waveform diagram shows the video signal S for one scan, where F is the ground level corresponding to the brightness of the normal part of the object to be inspected 3, and this ground level E has various values as is well known. Low frequency fluctuations appear due to these factors. Further, n is a defect signal corresponding to the pinhole 4 of the inspection object 3, and since strong light enters the imaging device v11 through the pinhole 4,
The defect signal n becomes a pulse-like signal with a level higher than the ground level F.

In order to discriminate this fault signal @n, the video signal ■S is binarized using an appropriate threshold value, but as is well known as floating binarization, the video signal VS is appropriately integrated and By appropriately level shifting, the video signal v
Threshold signal SH that follows fluctuations in ground level E during S
is created, and binarization is performed using this. FIG. 3 shows a specific example of the above-mentioned integrating circuit which is a main part of the circuit for obtaining the threshold signal SH. In this circuit, when the video signal VS is applied to the cathode side of the diode D, and the instantaneous voltage of the video signal VS is higher than the charging voltage Vc of the capacitor C (which is the output voltage of this circuit), the capacitor is connected through the diode D and the resistor R1. A charging current flows to C, and when the instantaneous voltage of the video signal vS is less than the voltage VC, a discharging current flows from the capacitor C to the resistor R2. Here, resistors R1 and R2
If the time constant of the charging path for the capacitor C is set to be relatively small and the time constant of the discharging path to the capacitor C is set to be relatively large, the output signal VC will be at a low frequency of IJ and ground level E as shown in Figure 2. The waveform follows the fluctuations of n and does not respond much to the pulsed defect signal n. A threshold signal SH slightly larger than the ground level E can be obtained by amplifying this signal VC appropriately or by adding a constant voltage to shift the level.

The above are the basics of defect discrimination. By the way, the m image system [11
As is well known, the output includes a period (corresponding to a retrace period, herein referred to as a blank period) in which no video signal is present between each scan. During this blank period, the charge in the capacitor C of the integrating circuit is discharged, so the integrated output VC gradually decreases, and the threshold signal S l
-1 also decreases.

In order to prevent erroneous discrimination due to a decrease in the threshold value during this blank period, conventionally, as shown in Figure 4, a gate G is provided in the charging/discharging circuit of the capacitor C, and this gate G is turned off during the blank period. The charging voltage VC of the capacitor C is held at the value i before the blank period. However, even with this circuit system, if the blank period in which the video signal VS is interrupted is long as shown in Figure 5, the voltage of the capacitor C cannot be completely held, and the voltage VC will decrease due to discharge.
gradually decreases. Therefore, it has not been possible to completely prevent malfunctions from occurring at the beginning of the video signal of the next scan due to an unnecessary drop in the threshold value SH during the blank period.

In addition, in the waveform example shown in FIG. 2, if the width and level of the fault signal @n are large, the charging voltage Vc of the capacitor C
is greatly influenced by the defect signal n, the voltage Vc rises unnecessarily, and the threshold value SH deviates greatly from the ground level E of the video signal vS. A problem has arisen in that even if a relatively small level of defect occurs immediately after, it cannot be detected.

This invention has been made in view of the above-mentioned conventional problems, and its purpose is to be completely unaffected by the blank period of each scanning amount of a video signal, and to be able to avoid being affected by the level and width of defective signals in the video signal. It is an object of the present invention to provide a defect detection device which can obtain a threshold value that is not influenced by the ground level of a video signal and correctly follows the ground level of a video signal, and as a result, can perform highly accurate defect discrimination with fewer erroneous discriminations.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 6 is a block diagram showing an embodiment of the defect detection circuit O according to the present invention, and FIGS. 7 and 8 show signal waveforms of each part of this defect detection device. The image pickup device 5, which is a COD image sensor or the like, operates in response to a control signal from the drive circuit 12, and photoelectrically moves over the inspection object 3 in the manner shown in FIG. 2, for example.

Scan repeatedly.

The video signal S output from the image sensor 5 and amplified by the amplifier 6 is level-compared with the threshold signal @sH obtained in the manner described in the defect discrimination comparator 16, and is thereby converted into a binary signal. The converted discrimination signal OUT is output.

The defect detection device according to the present invention includes an up/down counter 11, a D/A converter 14 that converts the digital counting output of the counter 11 into an analog signal, and an output signal of the D/A converter 14 and the above-mentioned image. The counter 11 is incremented at a predetermined speed according to the output C of the comparator 7 when vS>b, and when vS<b. is configured to count down at a predetermined speed, and to prohibit the counting operation of the counter 11 during a blank period for each scanning amount of the image carrier 5 and during a period when a defect is detected by the defect discriminating comparator 16. It is configured. The output signal S of the D/A converter 14 is appropriately amplified by an amplifier 15, and the output signal is used as a threshold signal SH.

To explain the embodiment in detail, the timing circuit 13 outputs two-phase clock signals TI and T2 that are synchronized with the scanning clock signal of the imaging element 5 produced by the drive circuit 12. As shown in FIG. 7, the clock signal @T2 is an extremely narrow pulse signal that occurs immediately after the fall of each pixel pulse included in the video signal VS, and the clock signal T1 is a clock signal It is also a narrow pulse signal that is generated very slightly apart from the signal T2. These clock signals TI and T2 are generated only during the period when the image sensor 5 is being scanned, and are not generated during the blank period of each scanning amount.

The output signal C of the comparator 7, which compares the levels of the video signal vS and the output signal W of the D/A converter 14, is sent to the flip-flop 8.
The clock signal T1 is applied to the reset input side of the flip 70 tube 8.

As a result, when the level of the 6-bar picture element pulse in the video *4g VS is higher than the level of the signal, a pulse signal is generated from the comparator 7 as shown in FIG. Set. Conversely, the video signal V
If the level of a certain pixel pulse in S is lower than the signal
The output signal C of the comparator 7 remains at L level, and the flip 7
0Tub1 remains reset by the clock signal T1. The set output Q of the flip 70 knob 8 is input to the AND gate 9, and the reset output Q is input to the AND gate 1.
It is input to 0. The clock signal T2 from the timing circuit 13 and the output OUT of the defect discrimination comparator 16 are connected to the two AND gates 9 and 10, respectively, through an inverter 17.
The inverted signal is input. And gate 9
The output signal of the AND gate 10 becomes the up-count input of the counter 11, and the output signal of the AND gate 10 becomes the down-count input of the counter 11.

In the above configuration, when the level of the video signal vS is lower than the threshold signal SH (in this embodiment, VS>SH is a defect signal), the output signal 00 of the defect discrimination comparator 16 is L Therefore, the signal inverted by inverter 17 becomes H level, which is applied to AND gate 9.10. In this state, if the level of each pixel pulse in the video signal VS is higher than the output signal of the D/A converter 14, the flip 70 knob 8 is set every time such a pixel pulse is generated. Each time a pulse signal UP is output from the AND gate 9, the counter 11 is incremented by one each time. Therefore, the level of the signal obtained by analog converting the output of the counter 11 also increases.

Contrary to the above, if the level of the pixel pulse in the video signal VS is lower than the signal level, the flip 7O knob 8 remains reset and the clock signal T2 is generated in that state, so the level of the pixel pulse in the video signal VS is lower than that of the signal. Every time a low pixel pulse occurs, a pulse signal DW is output from the AND gate 10,
Each time, the counter 11 is counted down by one.

As a result, the level of the signal obtained by analog converting the output of the counter 11 also decreases.

As described above, if the level of the video signal vS is higher than the signal S, the level of the signal S is increased, and conversely, if the level of the video signal vS is lower than the signal S, the level of the signal S is decreased. As a result, the output signal of the D/A converter 14 becomes approximately equal to the envelope signal of the video signal VS. What should be noted here is that the timing circuit 13
Tsuk signal T1. T2 is the blank period s l of the image sensor 5
Since it does not occur in -, the counting operation of the counter 11 is prohibited during the blank period BL. Therefore, there is no change in the level of the signal S during the blank period 8L, and the level at the end point of the video signal vS is maintained without decreasing at all. This situation is shown in FIG. 8(a). Since the threshold key signal SH is generated based on this signal, there is no level capital reduction during the blank period BL of the threshold value SH.

When a defect signal n is included in the video signal vs, this is detected by the defect discrimination comparator 16, and the defect signal n is detected by the defect discrimination comparator 16.
Correspondingly, the output signal 0LIT of the comparator 16 becomes H level. Then, from the inverter 17, the AND gates 9, 10
The signal applied to the counter 11 reaches the next level, and the counter 11
No count input is applied to the count input, and the count operation is prohibited. That is, comparator 16
- When the defect signal n is detected, the counting operation of the counter 11 is prohibited, and the signal b (L, key signal SH
) no longer changes and is held at the level immediately before the defect was detected. Therefore, as shown in FIG. 8(b), even if the video signal vS contains a defect signal n having a large level and width, the threshold value SH will not be unnecessarily fluctuated thereby. Even if a small defect signal occurs immediately after the large defect signal, it can be reliably discriminated.

In addition, in the above embodiment, the discrimination of a defect signal whose level is higher than the ground level E of the video signal vS was explained, but it goes without saying that the discrimination of a fault signal whose level is lower than the ground level E is similar to the above. .

As explained in detail above, the defect detection device according to the present invention is advantageous in that it uses an up-down counter instead of an integrator circuit including a capacitor to obtain an envelope signal that follows ground level fluctuations of a video signal. to digitally obtain data that follows the ground level signal of the video signal, and convert this using a D/A converter to obtain an envelope signal.
Moreover, since the counting operation of this counter is prohibited during the blank period and the defect detection period, unnecessary and harmful fluctuations in the threshold value during the blank period and the defect detection period are eliminated, and accurate defect detection can be performed.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the outline of the defect detection device, Fig. 2 is a diagram showing an example of the waveform of a video signal, Fig. 3 is a diagram showing the main parts of a conventional circuit for obtaining a threshold key signal, and Fig. 4 The figure shows the main parts of a conventional circuit for holding the threshold level during the blank period, and FIG. 5 is a waveform diagram showing problems with the circuit of FIG. 4.
FIG. 6 is a block diagram of an embodiment of the defect detection apparatus according to the present invention, and FIGS. 7 and 8 are diagrams showing waveforms of various parts of the apparatus according to the present invention shown in FIG. 5...Image sensor 7...Comparator 11...Up/down counter 14...
・D/A converter 16...Flaw discrimination comparator vS...Video signal SH...Threshold key signal 0LJT...Flaw discrimination signal Patent applicant Tateishi Electric Co., Ltd. Figure 1 Figure 2 Figure 3 R1 Figure 4 @ Figure 5 Figure 7 Figure 8

Claims (1)

[Claims] (1) A device that detects defects on the surface to be inspected by photoelectrically scanning the surface to be inspected with an imaging means and comparing the levels of the obtained video signal and an appropriate threshold value with a defect discrimination comparator. an up/down counter and a D/A that converts the digital counting output of this counter into an analog signal.
A converter and a comparator for comparing the level of the output signal of the D/A converter and the video signal a are provided, and the counter is set to a predetermined value when a>b according to the output of the comparator. It is counted up at a speed, and when a<b, it is counted down at a predetermined speed.
The circuit is configured to prohibit one count operation of the counter during the period when a defect is detected, and the output signal of the D/A converter is appropriately amplified, attenuated, or level-shifted to adjust the threshold value. A defect detection circuit characterized by obtaining a signal.