JPS585833A - Confirmation circuit for contents of data - Google Patents

Abstract

PURPOSE:To confirm the precise updata of data by automatically detecting whether data in the input and output sides of a storage circuit coincide each other or not and, in case of inconsistency, generating an alarm. CONSTITUTION:Input and output signals of a memory 2 are inputted to exclusive OR circuits 9a-9n respectively and outputs of the exclusive OR circuits 9a- 9n are inputted to an AND circuit 10. If an input signal of the memory 2 is different from its output signal at the updata of data, an alarm signal is generated from an output of the AND circuit. The alarm signal is inputted to an alarm circuit 11 and an alarm is sent from the circuit 11.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data content confirmation Ig circuit in a seeding setting circuit used in a remote monitoring and control device.

Figure 1 shows a conventional example for one channel of a remote monitoring and control device;
1 is a coding setting switch section for data setting, and this switch section 1 is formed of a plurality of switch groups SW, to 8Wn. Switch unit 1 includes switch groups sw1 to 8wn
When an arbitrary switch is closed, a coded predetermined value is output, and the set value (data) is input to the input buffer memory 2. The data input to the memory 2 is an update command signal (hereinafter referred to as BUI) generated when the update command generator is operated to change the number of days by operating the block switch 3.
i! (referred to as a signal) is stored in the storage memory 2. The stored nine data are outputted from the memory 2 and inputted to the parallel-to-serial conversion circuit (hereinafter referred to as P78 circuit) 4. This one
? The BUOY signal is supplied to the /B circuit 4, which is repeated at the period of time to insert the data and the BUOY signal, and is input as a serial signal to the serial/parallel conversion circuit (hereinafter referred to as 8/PIg1w!) 6 via the transmission line 5. be done. This s/P
(b) The line 6 converts the serial signal into a parallel signal, and the data of the signal is supplied to the output buffer memory 7.
The UOY signal is supplied to the determination unit 8 only when the strobe switch 3 is not operated (BUOY signal). If there is an OK signal input to the B/P circuit 6 and outputted when there is no transmission error in the nine series signals, the determination section 8 sends an MJIIMO signal to its output. When this MIMO signal is applied to the output panzer memory 7, the output panzer memory 7 stores the data and sends the data to the output. In other words, the contents of the memory 7 have been updated.

In the conventional encoding setting circuit configured as described above, when changing data using the encoding setting switch 1 and storing it in the output buffer memory 7, the conventional encoding setting switch 1 and the switch group 8 W l-8W
n cannot be operated at the same time, so in order to prevent erroneous data from being stored in the output button 7ar memory 7 during data setting, data is first put into the input capacitor 7ar memory 2, and then steps are taken to operate the strobe switch 3. Therefore, if the operator forgets to operate the strobe switch 3 after changing the data, the data will not be stored in the input buffer memory 3. Since then, the data is not sent to the data line output buffer 7, so there is a possibility that the contents of the output buffer memory 7 may remain unchanged.

Note that in the above circuit, the BUOY signal is input to
This is a signal that prevents the data generated by w4, which is currently updating the contents of the archive memory 3, from being transmitted and stored in the output buffer memory 7. Therefore, as mentioned above, 8/P circuit 6 to B
Give the USY signal to the determination unit 8 to ensure that the strobe switch 3 is in operation 4P! By updating the contents of the output buffer memory 7 only when the data has been changed, it is possible to send out the fact that the data has changed. However, if the strobe switch 3 is not operated as described above, the above-mentioned problem will occur.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a data content confirmation circuit that can confirm whether or not data has been updated accurately.

One embodiment of the present invention will be described below with reference to Figure RFIT--, in which the same parts as the first embodiment are denoted by the same reference numerals.

In FIG. 2, input and output signals of input buffer memory 2 are input to determination circuit 9. In FIG. This determination circuit 9 is composed of exclusive ORs 9a to 9n and an AND 10. The input and output signals of the memory 2 are respectively supplied to the inputs of exclusive ORs 91 to 9n, and the exclusive ORs 9
Outputs 1 to 9n are input to the logic ram 10. With this configuration, when data is changed, the memory 2
0 If the input and output signals (data) are different, the logical product is 100
A warning signal is sent from the output. The visual signal is input to the circuit 11, and an alarm is sent from the circuit 11 to instruct that the operator is not operating the strobe switch.

Since the determination circuit 9 and the alarm circuit 11 as described above are generally used, when data is changed, it is reliably transmitted to the output buffer memory 7 and its contents can be changed.

As described above, according to the present invention, it is automatically detected whether or not the data on the input and output sides of the memory circuit match, and when the data do not match, Fi, soy @ is emitted. Therefore, it has the advantage of being able to confirm that the data has been updated.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional example, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1... Encoding setting switch section, 2... Input bag 7
Arm memory, 3... String switch, 4...P
/ 1 circuit, 6-8/P (ro) path, 7-・Output 7
Arm memory, death,, determination unit, 9... determination circuit, 11-
...Alarm circuit.

Claims (1)

[Claims] (1) A group of hooded setting switches for data settings,
a memory circuit into which data set by the switch group is input; an update command generator which is supplied to the memory circuit and generates a signal for updating the input data; and a data input side of the memory circuit. a circuit that determines whether the supplied data matches the input/output side; and an alarm generation circuit that issues an alarm to prompt the update sound generator to operate if the determination result of this determination circuit is negative. A data content confirmation circuit comprising: