JPS5857928B2 - Tuning control method for frequency synthesizer receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel selection control method for a PLL (phase-locked loop) synthesizer receiver, and particularly to a programmable channel selection control system with a variable frequency division ratio that constitutes a part of the PLL circuit of a frequency synthesizer receiver. The present invention relates to a channel selection control method for a frequency synthesizer receiver that operates in conjunction with a divider and can detect and receive the broadcast wave with the best reception condition when the same broadcast content is transmitted at a plurality of frequencies.

Specifically, Japan Short Wave Broadcasting (NSB) is a broadcasting system that has multiple channels, each with different broadcast content, and in which the broadcast content of each channel is transmitted on multiple frequencies.
), and the first channel (first program) has 3. ．．
925,6055° using 9595 MHz, and in the second channel (second program) 3945,6115
．． They use 9760MHz and broadcast the same content.

In such a broadcasting system, in any broadcast receivable area, the listener can operate as necessary to determine the best reception condition among multiple broadcast waves transmitting the same broadcast content, that is, the electric field strength. The ability to detect and listen to broadcasts at the strongest frequencies is extremely beneficial.

SUMMARY OF THE INVENTION An object of the present invention is to provide a new channel selection control method for a frequency synthesizer receiver, which was created in view of the above-mentioned points.

The invention will be explained in detail below with reference to illustrated embodiments.

The illustrated embodiment is a frequency synthesizer receiver that can be used in a broadcast system in which two channels CH1 and CH2 have different broadcast contents, and the broadcast contents of each channel are transmitted using at least two broadcast waves. It is configured as a channel selection control method for

The frequency synthesizer section 1 basically comprises a known prescaler type PLL circuit.

That is, a local oscillator VCO, a prescaler (1/P frequency divider) ps, and a programmable divider PD.

A PLL circuit is configured by a phase detector PH and a low-pass filter LPF, and the oscillation frequency of the local oscillator VCO is controlled by a data signal (shown as a program signal = n bits) as described below, which is supplied to a programmable divider PD. , the desired frequency is received.

In addition, AT is an antenna, RF is a high frequency circuit, MIX is a mixing circuit, IF is an intermediate frequency amplification circuit, O8C is a reference oscillator,
D indicates a divider.

The output of the frequency synthesizer section 1, that is, the output of the intermediate frequency amplifier circuit IF, which is a received signal, is connected to be applied to the speaker SP via the low frequency amplifier AMP.

Each of the switches SW and SW2 is a channel selection switch that includes an appropriate pulse generation circuit (not shown) that generates a pulse signal when switched to the ON state. The broadcast waves of the second channel CH2 become receivable, and the ON state of the switch SW2 makes it possible to receive the broadcast waves of the second channel CH2.

The first read-only memory IJROM has a first channel C
Multiple frequencies transmitting H1 broadcast content (e.g.
Japan Shortwave Broadcasting: 3925, 6055, 9595MHz
), and on the other hand, the second read-only memory IJROM2 stores program data corresponding to a plurality of frequencies (for example, 3945.6 for Japan Short Wave Broadcasting) that transmit the broadcast contents of the second channel CH2. ,115.9760
MHz) is stored.

First and second memories ROM1. The data in the ROM2 are each addressed by an address signal (shown as m bits) given from the output 0UTc of the first counter CNT□, and the data signal read from the memory OUTM190UTM2 is used to operate the frequency synthesizer section 1. selectively provided to the programmable divider PD.

When the switch SW2 is previously in the ON state and a certain broadcast wave of the second channel CH2 is being received, when the switch SW1 is turned on in order to newly receive the broadcast wave of the first channel CH1. , flip-flop F
F1 is set and at the same time flip-flop FF2 is reset.

For one-man operation of AND gate G1, flip-flop F
Since F3 is in a reset state and its Q3 output is given in a high state, the pulse signal given by the ON state of switch SW1 is applied to OR gates GG, AND gate G, and OR gate G. Counter C via gate GG2
It is applied to the input IN of NT1.

As a result, an address signal is generated from the output 0UTc of the counter CNT, and an appropriate data signal is read from the memory ROM1.

Therefore, since the Q1 output of the flip-flop FF1 is applied to one input of the AND gate G2, the read data signal is transmitted to the AND gate G2. OR gate GG
3 to the programmable divider PD of the frequency synthesizer section 1, and a certain broadcast wave of the channel CH1 corresponding to the data signal read out by the address signals from the counters C and NT1 can be received.

When the reception condition of the broadcast waves received as described above deteriorates, when the switch SW1 is turned on again, the pulse signal given thereby is transmitted to the OR gate GG,
AND gate G1. It is applied to the input IN of the counter CNT1 via the OR gate GG2, and counts up this counter.

Therefore, a new address signal from the output 0UTc of the counter CNT causes a different data signal to be read out from the memory IJROM1, and the broadcast wave (
However, the broadcast content will be the same).

Therefore, each time the switch SW1 is turned on, the broadcast waves of the channel CH1 are received one after another, and the broadcast wave with the best reception condition can be searched for.

On the other hand, the operation when the switch SW2 is in the ON state to receive the broadcast wave of the second channel CH□ is almost the same as the operation when the switch SW1 is in the ON state. Flop FF1 is reset, flip-flop FF2 is set at the same time, and the Q2 output of flip-flop FF2 is output from AND gate G3.
given to one person's strength.

Therefore, a certain broadcast wave of channel CH2 corresponding to the data signal read from the memory IJROM2 can be received by the address signal from the counter CNT□, and after that,
Each time switch SW2 is turned on, channel CH
By receiving two broadcast waves one after another, it is possible to deepen the broadcast waves with the best reception condition.

Next, instead of manual detection as described above, the operation when automatically detecting the broadcast wave with the best reception condition will be described below.

When the automatic detection switch SW3 is turned on, flip-flop FF3 is set and its Q3 output becomes high.

Therefore, the clock pulse output of the clock generator CK is
AND game 1-04. It is applied to the input IN of the counter CNT1 via the OR gate GG2.

At this time, due to the low state of the Q3 output of the flip-flop FF3, the switch SW is turned off, thereby preventing the output of the intermediate frequency amplifier circuit IF from being applied to the low frequency amplifier AMP.

The counter CNT1 counts up every input clock pulse and outputs address signals one after another.

As a result, according to the selective ON state of switch SW or SW2, data signals stored in memory IJROM1 or ROM2 are read out, and broadcast waves of channel CH1 or CH2 can be sequentially received.

The output of the intermediate frequency amplifier circuit IP is connected to the input of the waveform shaping circuit S, and each time a broadcast wave is received as described above, a reception level signal indicating the level value of the electric field strength is sent to the waveform shaping circuit S. is output from.

The level value of the broadcast wave received before that time is held in the level holding circuit H.

The comparator COMP compares the level value of the level holding circuit H and the level value of the received signal output from the waveform shaping circuit S, and when the level value of the received signal is larger than the level value of the level holding circuit H, The output of comparator COMP goes high.

At this time, the second input of AND gate G is in a high state at the Q output of flip-flop FF3, so the latch circuit is energized and addresses the data signal corresponding to the broadcast wave being received there. Output 0 of counter CNT1
Signals from UTo are stored.

The output of the AND gate G also switches the switch SW4 to the level holding circuit H side, and the output of the waveform shaping circuit S is held in the level holding circuit H as a new level value, that is, the highest level value up to that point.

The second counter CNT starts counting upon receiving the clock pulse output from the clock generator CK at the same time as the switch SW3 is turned on, in other words, due to the low state of the Q3 output of the flip-flop FF3.

Counter CNT2 is the count or memory IJROM□
Alternatively, when a preset value corresponding to the number of times of addressing all the broadcast wave data stored in the ROM 2 is reached, an output signal is generated.

This output signal of the counter CNT2 is applied to the preset power P of the counter CNT1, which causes the counter CN
The address signal of the data signal indicating the highest level broadcast wave stored in the latch circuit provided to the program input PG of T1 is obtained as the output of the counter CNT□.

As a result, the broadcast wave with the best reception condition can be received.

The output signal of counter CNT2 is also applied to the reset input R3 of flip-flop FF3, causing its Q3 output to go low and its Q output to go high.

The low state of the Qj output is determined by the AND gate G4. G5 and display m■ND are deenergized, and the high state of Q output is indicated by counter CNT.
2 and switch SW to enable listening to the received broadcast waves.

Note that the indicator IND is a visible indicator that lights up when the flip-flop FF3 is set, and indicates that the device of the present invention is in a mode in which it is detecting a broadcast wave with the best reception condition.

According to the present invention, it is possible to extremely easily and quickly detect the broadcast wave with the best reception among broadcasting systems in which the same broadcast content is transmitted using multiple broadcast waves. The present invention is most suitable as a channel selection control system for mobile receivers such as car radios.

When the present invention is applied to the reception of Japanese shortwave broadcasting, for example, the address signal output from the counter CNT is processed by an appropriate decoder, and a display corresponding to the broadcast wave usually called 3°6.9 MHz is generated. It is also possible to configure the lamp to be selectively turned on.

Further, although the illustrated embodiment shows a two-channel tuning control system, it is clear that it can be extended to a multi-channel tuning control system by parallelly installing memories, flip-flops, switches, etc. be.

[Brief explanation of drawings]

The figure is a block diagram showing an embodiment of the present invention. Symbol explanation, 1: Frequency synthesizer section, AT: Antenna, RFz high frequency circuit, MIX: Mixing circuit, ■F: Intermediate frequency amplification circuit, O8C: Reference oscillator, D: Divider, VC
O: local oscillator, PS nib scaler, PD: programmable divider, PH two-phase detector, LPF: low-pass filter, SWl. SW, SW3. SW4. SW5: Switch, FF1°FF, FF3: Frilob flop, CNT. 1 CNT2: Counter, ROM1. ROM2: Read-only memory, S: Waveform shaping circuit, L: Launch circuit, COMP
: Comparator, CK: Clock generator, IND: Display, S
P: speaker, AMP: low frequency amplifier. G1. G2. G3. G4. G5: AND gate, GG
l, Ga4, Ga3: OR gate.

Claims (1)

[Claims] 1. A frequency synthesizer, a plurality of switches respectively corresponding to a plurality of channels having different broadcast contents, and a plurality of switches associated with each of the plurality of switches and storing data signals respectively corresponding to a plurality of broadcast waves having the same broadcast contents. and a counter, and by selecting one of the plurality of switches and turning it on, the counter counts up and outputs an address signal, and the data corresponding to the address signal is output. a signal is read from the memory associated with the selected switch, and the read data signal is input to the PLL of the frequency synthesizer.
A tuning side selection system for a frequency synthesizer receiver, characterized in that a program signal is supplied to a programmable divider included in the circuit.