JPS5857771B2 - keyboard encoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dynamic keyboard encoder having an N-key rollover function and having good noise resistance.

Conventionally, in dynamic keyboard encoders, N
Key rollover function, when pressing multiple keys one after the other, such as pressing the next key before the previous key is released, encodes the corresponding encoded output in the order of the keys pressed. In order to achieve a function that can be stacked sequentially, there is a method that determines whether the key being pressed during the current scan was not pressed during the previous scan, and outputs a strobe signal based on the determination result. It has been adopted.

However, this method only detects the rise or fall of the output signal associated with the key press, and does not take into account the length of time the key is pressed. Because this is not done, in the rare case that a key is scanned while noise is picked up on the output line of a key, the rise or fall of the noise may be misinterpreted as a key press. There is a possibility that a strobe signal will be output.

Here, the inventor of the present invention found that the output signal caused by a key being pressed is a continuous signal over at least two scanning periods, whereas the signal caused by noise being picked up is a continuous signal over two scanning periods. This invention was made based on the knowledge that continuous detection over a period of time is extremely rare.

The purpose of this invention is to provide a dynamic keyboard encoder that distinguishes between signals from normal keys and noise based on the above knowledge, has an N-key rollover function, and has good noise resistance. It is something to do.

That is, the present invention includes a counter that outputs a key code, a scanning circuit that sequentially scans the output of each key in response to the output of this counter, and an output of each key that was output from the scanning circuit in the previous scanning cycle. a first storage means that outputs an output during the current scan; a second storage means that outputs the output of each key outputted from the scanning circuit in the scan period before the previous scan during the current scan; Set the output to 1st. A logic circuit that compares the output of the second storage means to determine that the key that is ON at that time was also ON during the previous scan and OFF during the scan before the previous one; The keyboard encoder is characterized by comprising a latch circuit that latches the output of the counter in response.

An embodiment of the present invention will be described in detail below based on the accompanying drawings.

In FIG. 1, row line Y.

-\3 and column line Xo-X3 constitute a keypad IJ circuit 1, and a key switch S is provided at each intersection.

0 to S33 are connected.

Each row line Y. One end of -Y3 is connected to the power supply Vc via a resistor R7, and the other end is connected to each input terminal of the multiplexer 2.

On the other hand, column line X. -X3 are connected to each output terminal "01 to "3" of the decoder 3, respectively.

The input terminals A and B of the decoder 3 are supplied with the upper 2 bits output Qc + QD (see FIG. 2) of a counter 4 that counts the basic clock from the clock pulse generator 5 (see FIG. 2), and the multiplexer 2 The input terminals A and B of the counter 4 have the lower two bits output QA, QB (second
(see figure) is supplied.

Therefore, each time the output of the counter 3 is switched, the output of the key 5OO=833 is output one by one to the output side of the multiplexer 2.

At this time, for example, if key S2° is pressed,
The output of multiplexer 2 becomes rHJ during the scanning period of key 821, as shown in FIG.

6 is a shift register (hereinafter referred to as the first shift register) having a capacity of 16 bits.

), and this first shift register 6 responds to the fall of the basic clock supplied to the shift input terminal CP, reads the output of the multiplexer 2 supplied to the input terminal A at that time, and shifts the entire clock to the right. It is configured to shift 1 bit to .

That is, on the output side of the multiplexer 2, each key 5OO=833 is turned ON every time the basic clock falls.

The OFF state signals are output one by one, and for example, in response to the falling edge of a certain basic clock, the output of the multiplexer 2 becomes S.

1 to S. 2, the signal from the key 801 before switching is read into the first shift register 6 in response to the fall of the basic clock.

The first shift register has a 16-bit capacity, and since the ON/OFF state signal corresponding to the same key is outputted to the output side of the multiplexer 2 every 16 cycles of the basic clock, the state of each key can be repeatedly scanned. Then, as shown in FIG. 2, the state signal from the previous scan of the key that is being output from the multiplexer 2 at that time is output to the output side of the first shift register 6.

7 is a shift register (hereinafter referred to as the second register) having a capacity of 16 bits.

), this second shift register 7 responds to the fall of the basic clock supplied to the shift input terminal CP, reads the output of the first shift register 6 supplied to the input terminal A at that time, and is configured to shift 1 bit to the right.

In other words, the second shift register 7 has a 16-bit capacity, and the output side of the second shift register 6 outputs the state signal of the previous scan of the key that is output from the multiplexer 2 at that time. When the state is repeatedly scanned, the state signal from the previous scan of the key outputted from the multiplexer 2 at that time is outputted to the output side of the second shift register 7, as shown in FIG. 2O.

8 is a latch circuit that latches the output of counter 4;
The latch circuit 8 is configured to perform a latch operation in response to the rising edge of the output of the AND gate 9 supplied to the clock input terminal CK. Register 6 and 2nd
The outputs of the shift register 7 are supplied in parallel.

Note that 10 is a NOT gate for inverting the output of AND gate 9 to obtain a strobe signal, and 11 is a second gate.
NOT to invert the output of the register and inhibit AND gate 9, thereby achieving the N-key rollover function.
It is a gate.

In the above configuration, when a certain key (for example, 521) is pressed, a certain scanning period (hereinafter referred to as a first scanning period) is generated.

), it is assumed that the output of the multiplexer 2 becomes rHJ for the first time at the scanning timing of that key.

At this time, the output rLJ of the key S21 during the previous scan is output from the first shift register L as shown in FIG.
As shown in FIG. 2, the output is prohibited, and no strobe signal is output.

Furthermore, it has been empirically confirmed that when a key is pressed normally in this manner, the output of the multiplexer 2 becomes rHJ at the scanning timing of the key for at least two scanning periods or more.

Therefore, the next scanning period (hereinafter referred to as the second scanning period).

), the output of the multiplexer 2 and the output of the first shift register 6 are both rHJ, and at this time, the inverted value of the output of the second shift register 7 is still rHJ as shown in FIG. For this reason, all inputs of the AND gate 9 become 1-HJ, and the output of the AND gate 9 becomes rHJ for the first time as shown in FIG. 2G.

Then, at the rise of the output rHJ of the AND gate 9, the key code of the key S21 is latched in the latch circuit 8, and the output of the AND gate 19 is inverted by the NOT gate 110 and becomes the strobe signal. is output as

On the other hand, in each scan period after the third scan period, the second shift register 7 at the scan timing of the key S21
The inverted values of the outputs are all rLJ as shown in FIG. 2 O.

Therefore, the output of the AND gate 9 is inhibited by this rLJ, and all strobe signals in subsequent scanning cycles are inhibited, thereby achieving the N-key rollover function.

Next, suppose that noise is picked up at the scanning timing of the key SO2 in the second scanning period, and the output of the multiplexer 2 becomes "H" as shown in FIG.

At this time, since the output of the first shift register 6 is "L" as shown in FIG. 2, no strobe signal is output.

Here, due to noise, multiplexer 2
It has been empirically confirmed that it is extremely rare for the rHJ signal to be output at the same scan timing in successive scan periods when the output of the rHJ signal becomes "H".

Therefore, the key S in the third scanning period.

At the scanning timing of 2, the output of the first shift register 6 becomes rHJ, but the output of the multiplexer 2 becomes "L", so the output of the AND gate 9 is prohibited by this rLJ signal, and the strobe signal is is never output.

In other words, the strobe signal will never be output depending on the multiplexer output rHJ due to noise being picked up.

Although shift registers are used as the first and second storage means in this embodiment, it is of course possible to replace these with RAM.

As is clear from the above description, the present invention includes a counter that outputs a key code, a scanning circuit that sequentially scans the output of each key in response to the output of this counter, and a counter that outputs a key code. a first storage means for outputting the output of each key during the current scan; a second storage means for outputting the output of each key output from the scanning circuit in the scan period before the previous scan; The output of the above-mentioned scanning circuit is sent to the first . A logic circuit that compares the output of the second storage means to determine that the key that is ON at that time was also ON during the previous scan and OFF during the scan before the previous one; Since it consists of a latch circuit that latches the output of the counter in response, it is possible to reliably distinguish between a normal signal from a key and noise, and thus it has an N-key rollover function and is noise resistant. Therefore, it is possible to provide a dynamic keyboard encoder with good performance.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the electrical configuration of a keyboard encoder that is an embodiment of the present invention, and FIG. 2 is a diagram showing waveforms at various parts on the circuit diagram. 2.3... Scanning circuit, 4... Counter, 6... First storage means, γ... Second storage means, 8... ...Latch circuit, 9, 11...
...Logic circuit, 5OO-83, 1... key.

Claims (1)

[Claims] 1. A counter that outputs a key code, a scanning circuit that sequentially scans the output of each key in response to the output of this counter, and a scanning circuit that sequentially scans the output of each key in response to the output of this counter, and a scan circuit that scans the output of each key output from the scanning circuit in the previous scan period during the current scan. a first storage means for outputting an output, a second storage means for outputting the output of each key outputted from the scanning circuit in the scanning cycle before the previous time during the current scanning, and a second storage means for outputting the output of the scanning circuit for each scanning cycle, ．． Second
Compared to the output of the storage means, that! A logic circuit that determines that the key that is ON was ON during the previous scan and OFF during the scan before the previous one, and a latch circuit that latches the output of the counter in response to the output of this logic circuit. A keyboard encoder comprising: