JPS5857766B2 - Speed and phase control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to servo devices, and more particularly to servo devices using digital technology.

Servo systems for motors, such as those used in video recorders, require considerable precision in terms of the temporal stability of the video signals to be processed.

Furthermore, a digital servo device is desired from the viewpoints of high precision, low cost, and high stability.

When digitizing a servo circuit such as a VTR, it is easy to follow the same system configuration as an analog servo.

FIG. 1 shows an example of a conventional digital servo having a digital speed detector 10 and a digital phase detector 12, each of which is provided with DA converters 11 and 13.

The output of the FG 16, which generates a signal representing the rotational speed of the motor 14, which is the controlled object, is given to the speed detector 10, and then the analog output from the DA converter 11 is given as X to the circuit point 18.

- the output from the FG 20 producing a signal representative of the force, rotational position or phase of the motor 14 is phase compared in the digital phase detector 12 with a reference phase input pulse at the terminal 22;
This output is then converted into an analog signal y by a DA converter 13, and then subtracted from the signal X at a circuit point 18.

The output from circuit point 18 is provided to motor 14 via motor drive amplifier 24.

If the configuration of such an analog type servo is simply digitized, it is easy to add and subtract analog voltages and currents, making it easier to set constants, but on the other hand, it is necessary to expand the phase detection range to increase the target setting speed and the response speed. When trying to improve the DA converter, one condition is imposed on the DA converter.

That is, the maximum operating range of the DA converter 13 is
If the maximum operating range is exceeded, there is a possibility that abnormal operation will occur during transient operation.

Furthermore, if the speed detector 10 is unable to subtract the excessive error of the phase detector 12, the excessive error is amplified into a super loop error, which may cause transient oscillation or lock-in failure.

Therefore, in the configuration shown in FIG. 1, the dynamic range, that is, the resolution, of the DA converter 11 is normally required to be sufficiently narrow.

Similarly, instead of arranging the DA converters 11 and 13 after the speed and phase detectors 10 and 12, a digital adder 26 for adding the digital outputs of the respective detectors 10 and 12 is provided. The same can be said about the configuration shown in FIG.

In adder 26, the output of speed detector 10 is subtracted from the output of phase detector 12.

The output of the adder 26 is converted into analog form by a DA converter 28 and applied to the motor 14 via a motor drive amplifier 24.

If the number of bits of the output of the speed detector 10 and the output of the phase detector 12 are respectively m and n, then m and n are generally m
The condition ≧n is required, and therefore, in order to increase the transient approach speed, m must be increased as well as the number of bits of n, which naturally leads to an increase in the scale of the speed detector and adder. Become.

The present invention utilizes the conventional digital
This eliminates the above-mentioned drawbacks of the servo system, and FIG. 3 shows the principle of the present invention.

The rotation of a controlled object such as the motor 14 is F, G16 and P.
Detected by G20.

The output of the FGI 6 is given to a speed detector 10, this digital output is converted into an analog signal J by a DA converter 11, and then sent to the motor 1 via a motor drive amplifier 24.
given to 4.

- force, the output of PG 20 is phase compared with a reference phase human pulse at terminal 22 in a phase detector, and this output is applied to speed detector 10 as a window shift signal.

In this configuration, the maximum control range (3) of the phase detector is larger than that of the speed detector (J).

As a result, a large detection output K is generated during transients, which shifts the speed detection constant (width/window position), instantaneously causes a transient error, and rapid acceleration is obtained, but the speed of the controlled object is sufficient. After shifting to , the speed will again be within the speed window, so the target point will be approached within a certain speed limit.

According to this configuration of the present invention, there is no problem of large-amplitude medium-region instability due to approach only in the position feedback loop, which can occur with the configurations of FIGS. 1 and 2.

FIG. 4 shows an embodiment in which the principle of the present invention shown in FIG. 3 is embodied in a capstan servo circuit of a VTR.

The main purpose of the capstan servo is to record a CTL signal on the tape during recording and frame it during playback to obtain stable tape running and reproduced images. Servo operation with a wide dynamic range is expected to achieve fine speed control and high-speed framing.

The capstan servo circuit in FIG. 4 basically has three parts: a speed control circuit part 100 and a phase control circuit part 10.
2. It consists of a clock signal generation circuit section 104.

The speed control circuit section 100 includes four cascaded preset type 4-bit color circuits 106, 108, 11.
Contains 0,112.

These counters have a load input LO that receives a load command from the load pulse generation circuit 114 and a clock input CK that receives a clock signal from the clock signal generation circuit portion 104.

The clock signal generation circuit portion 104 is 14.31818
MHz (four times the frequency of the NTSC color subcarrier) crystal oscillator, whose output is F
It is synchronized with the G signal.

A 105-tooth FG (frequency generator) is provided on the shaft of the capstan motor, and its output is fed to a differential slice amplifier 120 via terminals 116 and 118, where it is converted into a zero-cross pulse, and further 1 The frequency is divided by 1/2 by the /2 counter 122 and applied to the data (D) input of the D-type flip-flop 124.

- the clock (CK) of this flip-flop 124;
Since the clock signal of the oscillator 104 is applied to the input, the Q output of the flip-flop provides a timing edge synchronized with the clock signal of the FG signal whose frequency has been divided into 1/2.

This synchronization signal is applied to a load pulse generation circuit 114 in the form of an edge differentiator circuit.

The counter circuits 106 to 112 have a total counting capacity of 16 bits, and the phase control circuit section 102 is connected to the load input LO.
The data and fixed data on the line group 12G from the oscillator 104 are preset, and the clock signal from the oscillator 104 is counted.

The second, third and fourth counters 108, 110, 112 each have a digital output terminal MAX for maximum count value.

The MAX outputs of the third and fourth counter circuits 110 and 112 are given to an AND circuit 128, whose output is NAND
One input of circuit 130 and D-type flip-flop 13
It is given to the D input of 2.

The input of the NAND gate 130 is the second counter circuit 10
8 MAX output, and the upper two bit outputs of the first counter 106, the outputs of which are applied to the AND gate 134.

Another input to AND gate 134 is the clock signal from oscillator 104, the output of which provides the clock input for the counter.

D-type flip-flop 132 receives the 172FG divided pulse of D-type flip-flop 124 at its clock (CK) input.

The howl control circuit portion 100 also includes first and second 4-bit latch circuits 136 and 138.

These latch circuits receive the lower 8-bit outputs of the counter circuits 106 to 112, and the 8-bit latch outputs receive the D
A converter 140 is provided.

The output of the DA converter 140 is provided to the capstan motor via a morph drive amplifier.

The clock (CK) input of each latch circuit 136, 138 receives the 1/2 FG frequency divided edge pulse of the flip-flop 124, and the clear input (CR) receives the Q output of the flip-flop 132.

The AND gate 128, the NAND gate 130, the D-type flip-flop 132, and the AND gate 134 are operating range regulating circuits, and the upper 8 bits are all by ('1'').
The number smaller than the number is fixed as the minimum, and the number when the upper 14 bits are by and the position 2 bits are low is fixed as the maximum.

The former is achieved by providing the Q output of the flip-flop 132 to the clear (CR) input of each latch circuit, and the latter is achieved by providing the N
This is done by providing the output of AND gate 130 to AND gate 34.

The data applied to the counter circuit defines a 9-bit window, the center value of which is (100000000).

The lower 8-bit output of the counter circuit is given to the latch circuit, and the latch timing is performed by the 1/2 FG frequency division edge pulse.

As a result, the counter output during carry-up or carry-down is not latched at random timing, which eliminates the possibility of erroneously transmitting the transient state output before the end of carry-up or carry-down. Abnormal numbers will no longer occur.

Also, immediately after the latch pulse, the load pulse generation circuit 11
4, a load pulse is generated and the counter circuit is preset to the initial state.

The input data of the upper 7 bits of the counter circuit is fixed, and is set to (1001111) in this embodiment.

Therefore, the initial state is (10011110ooooo oo
oo+data).

The central initial state is a binary number (10011110000 oooo), decimal number 40704.

The MAX outputs of the third and fourth counter circuits are sent to the AND gate 128 as described above, so when the counter circuits are (11111111XXXXxxxx), the AND
The output of the gate 128 becomes by, and this state is applied to each latch circuit 136, 138 in synchronization with the 1/2 FG frequency division edge pulse in the D-type flip-flop 132 to release its clearing. .

Therefore, the count state is (11111111xxxx
xxxx), the latch output is valid only when

That is, it can be said that in the operating range (window) of speed detection DA conversion, the upper digit is at the position (11111111xxxx xxxx).

Further, the bi output of this AND gate 128 is also given to a NAND gate 130.

Since the NAND gate also receives the MAX output of the second counter 108 and the 3rd and 4th bit outputs of the first counter, A
An inhibit signal is provided to ND gate 134.

This prevents the count number of the counter circuit from overflowing during startup and the like.

Here, the reason why the counter circuit is not stopped at the state (1111111111111111) is that 70n
This is because it is assumed that one or two counts may be added from the time of detection until the stop is applied due to the circuit delay since the second output signal period is quite short.

Even at the cost of reducing the full scale by a few bits, the advantage of completely eliminating the risk of malfunction due to overflow is significant.

FIG. 5 is a graph diagram showing the operation of the speed control circuit portion 100 described above.

Level A is (1111111111111100), 6
5532 count position or level at which NAND gate 130 provides an inhibit signal to AND gate 134 and stops the clock signal to the counter circuit.

- force, downward level B is (11111111oooo
oooo), the count position is 65280, and at this level, the output of the D-type flip-flop 132 releases the latch circuit.

A-B is approximately 8 bits within the window.

This defines the output of the DA converter.

The center preset value given to the counter circuit is (100
1111100000000), the central count number xo at the center of the window is C(111111111
0000000), 65408 - center preset value + x
From the relationship o, xo=24704.

The count number of 24704 is 14. used in the example.
579.59Hz against a clock of 31818MHz
requires a gate spacing of

The counter circuit is loaded immediately after the latch, so 579
．． 59×2Hz becomes the FG center frequency.

Since the number of FG teeth is 105, the cat stan axis is 11.0.
Try to rotate at 40 revolutions per second.

As the rotation decreases, the latch interval widens, the count increases, and the motor is accelerated by the increase in DA output, achieving stable speed feedback.

Although an extremely coarse 8-bit DA converter is used here, the actual operational resolution can be made sufficiently fine according to the embodiment shown in FIG. 5, and the jitter due to quantization error can be made sufficiently small.

However, the maximum operating range of this speed control loop is ±128
/24704 characters ±0.5%, and if high-speed framing is activated, there is a possibility that it will deviate from the control range.

This can be avoided by combining the phase control circuit portion 102 as shown in FIG.

The operation of the phase control circuit section 102 changes the preset data to the counter circuit of the speed control circuit section.

The data center is (100000000), 256, which can be converted from (o oooo oooo) to (111
111111), the operating center of the speed control loop moves upwards by 256/24704, or approximately 1%.

Instantaneous data shift of ±128/24704 or more (
If there is a phase error), the control operation deviates from the linear region, but this is not accompanied by a transient phenomenon due to a super-recurrence error or the like, as is the case with the conventional configurations shown in FIGS. 1 and 2.

As mentioned above, by setting the shift amount of the window center to 11%, the acceleration range also becomes 11%, and even if this range is larger than the speed range, lock-in will not become impossible.

In FIG. 4, 142, 144, and 146 are phase detection counters each consisting of a preset type 4-bit counter and a D-type flip-flop, and constitute a 9-bit counter circuit.

This counter circuit is 14.31818 from the oscillator 104.
A clock signal obtained by dividing MHz to 1/40 by a circuit 148 is received at its clock (CK) input.

The reference field of the terminal 150 extracted from the video signal or formed from a synchronization board etc.■) The signal is 1/2 by the circuit 152.
Field delayed and synchronized with the reference frame signal at terminal 154 by D-type flip-flop 156, a 1/2 duty reference CTL pulse is produced at its Q output.

In the recording mode, this reference CTL pulse activates the CTL pulse generator 160 in response to the REC command at the terminal 158 to cause a recording current to flow through the CTL head 162.

The REC command signal at the terminal 158 is connected to the 4-bit latch circuit 16.
2, 164 and a D-type flip-flop 166 to maintain the outputs of circuits 162, 164 at 0 and circuit 166 at by, thereby keeping the load data line 126 in line 126 during recording. (100000000) to fix the window in the center state.

During reproduction, the CTL signal reproduced by the CTL head is amplified by the CTL pulse reproduction amplifier 168 and discriminated by the monostable multi 170.

This is 162°164.1 for each circuit of the 9-bit latch circuit.
This is the phase signal applied to the clock input of 66.

A reference CTL signal from a flip-flop 156 is applied to the load (LO) input of circuits 142 and 144 and the set input of circuit 146 in the 9-bit power counter circuit.

Therefore, at the 1/2 duty point of the flip-flop output, the counter circuit waits at all zero points.

This counter starts counting from the timing edge, and by providing an AND gate 172, the AND circuit output supplies its output to the enable (ENA) of the circuit 142 at the point where the upper 5 bits out of the total 9 bits become by. This is a usurpation that stops the count enable and stops overflow.

- The CTL playback output from the duck multi 170 causes the 9-bit latch circuit to latch and send the count number of the 9-bit power counter circuit to line 126 as load data.

Linear operating range from timing edge is 40/14 M
The time is approximately 1.4 msec at Hz x 9 bits, but since the counter circuit is loaded to O with 1/2 duty, the independence of the nonlinear region of phase detection is good.

[Brief explanation of the drawing]

1 and 2 are schematic block diagrams for explaining a conventional servo device, FIG. 3 is a schematic block diagram illustrating the principle of the present invention, and FIG. 4 is a schematic block diagram illustrating the principle of the present invention. A circuit diagram of an embodiment applied to a servo circuit, FIG. 5 is a graph diagram explaining the operation of the embodiment of FIG. 4. In the figure, 106, 108, 110, 112 are 4-bit counter circuits, 114 is a load pulse generation circuit, 128 is an AND circuit, 130 is a NAND AND circuit 2 is a D-type flip-flop, 134 is an AND gate, 136, 138
is a 4-bit latch circuit, 140 is a DA converter, 142
, 144 is a preset type 4-bit counter, 146 is a D-type flip-flop, 156 is a D-type flip-flop, 162 and 164 are 4-bit latch circuits, and 166 is a D-type flip-flop.

Claims (1)

[Claims] 1. A first n-bit counter that detects a first pulse signal indicating speed information of a controlled object and a second pulse signal indicating phase information and counts a reference clock signal; a latch circuit that latches the lower m bits of the output of the first n-bit counter; and a latch circuit that operates the latch circuit when the output of the first n-bit counter exceeds a predetermined minimum count value; A control circuit that stops supplying the reference clock signal to the first n-bit counter when the output of the n-bit counter reaches a predetermined maximum count value, and digital-to-analog conversion of the output of the latch circuit. A conversion circuit is provided to control the speed of the controlled object based on the conversion output, and a second bit counter is provided to output a bit corresponding to the phase difference between the second pulse signal and the reference phase signal. , and convert this to the first part above.
A speed and phase control device that performs phase control by loading an n-bit counter of the device. 2 The lower m-bit output from the first n-bit counter is digital-to-analog converted so that the lower m-bit output is obtained only when the controlled object is within the set speed range, and in other ranges. The n-bit counter is held at a substantially minimum value or maximum value, and the number of bits k of the second bit counter is set to m.
Speed and phase control device selected such that < k < n.