JPS5857692A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To ensure the correct reading of data regardless of the fluctuation of the power supply voltage, by charging directly the other end of a capacitor with the potential of a bit line which charges an end of the capacitor in a dummy cell of one transistor type memory. CONSTITUTION:Transistors (TR)Q16, Q17, Qn6, Qn7, etc. are connected to capacitors C12-Cn2 within a dummy cell DC'. The control signal DWL* of dummy word line is applied in common to each gate of TRs Q17-Qn7. At the same time, the bit line charge-up signal BC is also applied in common to each gate of TRs Q16-Qn6. The charge voltage VCC of bit lines -BL1 and -BLn is supplied to the other end of capacitors C12 and Cn2 respectively via TR Q16 and TR Qn6. The potentials of nodes N12 and Nn2 always follow the potentials of the lines -BL1 and -BLn. Thus the inconvenient differential voltage never occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memories, in particular to semiconductor memories of the one-transistor dynamic type.

One-transistor dynamic type semiconductor memory is being put into practical use.For example, "I EEEJOUR
NAL OIi' 80LID-8TATICCIRC
UITS, VOL.

5C-15,NO,2,APRIL 19 B OA6
4 kbit MO8Dynmmlc RAM wit
h Novel Memory Capacitor”
Proposals have been made as follows. This plum semiconductor memory has a memory cell (consisting of one transistor and a capacitor paired with it) connected to one bit line (BL), and a word line (WL) that turns on/off the transistor.
), the other bit M (BL) that is paired with the one bit 1ll (BL), a dummy cell (consisting of a capacitor) connected to the bit line (BL), and a dummy word M (consisting of a capacitor) connected to the capacitor. DWL) etc. (described later). Even in such a semiconductor memory, a normal sense amplifier is provided on the pair of the bit lines (BL, BL), and amplifies the voltage difference between the two lines to read out data. Eggplant. This differential voltage is level-compared with a predetermined constant reference voltage, and data ``1'' or ``0'' is read out depending on the level.
It does not necessarily take a fixed binary level depending on the OII. The main factor is power supply voltage fluctuation. If there is such a power supply voltage fluctuation, the BL line (BL)
) and (BL) will deviate from the specified values. As a result, erroneous data may be read. However, such power supply voltage fluctuations are unavoidable, and it is necessary to take measures to prevent the reading of erroneous data.

Therefore, it is an object of the present invention to propose a one-transistor dynamic type semiconductor memory that can always perform correct 7 r-reading even when there are fluctuations in the power supply voltage.

In accordance with the above object, the present invention is characterized in that the other end of the capacitor in the dummy cell is directly charged from the potential of the bit line of the capacitor in the dummy cell.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a circuit diagram showing a general one-transistor dynamic type semiconductor memory to which the present invention is applied. In this figure, C11 and Q15 are a capacitor and a transistor that constitute a one-) run sister dynamic type memory cell. This capacitor C1
1" of stored data depending on the presence or absence of optical TM for 1",
゛(B' switches 5y. One end of transistor Q+5 is pinned) +WI B 14 'l'-connection k I-...pin
The tip of -5BL reaches the sense an fSA. The word &WL for the bit line is tied to the date of the l-run transistor Q15. Hold Hince amplifier SA1 and click)
Pure BL1 is cloth assembled, and a dummy cell DC is placed at its tip.71. Ru. The capacitor CI is in the dummy cell C.
2 is provided, and the other end is a dummy word 1DW.
It is connected to the intermediate connection point of transistors Q6 and Q7 via L.

Dummy word control signals (*, *) are applied to the transistor Q7 (dar). A similar configuration is formed over multiple stages, and the n-th stage is illustrated. In other words, it is a lineage centered on Sense Anzo SAn. In addition, pairs of word iWL and dummy word line t are formed in many other stages, but these are not shown. The operation will be explained next.

2A and 2B are waveform diagrams used to explain the operation of the semiconductor memory shown in FIG. 1. FIG. 2A is for reading data tO'', and FIG. 2B is for reading data In FIG. 2A, before time t1, the bit line charge-up signal BC is at a level equal to or higher than the high potential power supply voltage ■cc (more precisely, ■co+■th+α, hereinafter referred to as V). C*),
The transistors Qll*Q12, Qa, etc. in FIG. 1 are on. Here, p) iBL and BI,
(BLl...BLn and BI4-BL in Figure 1
nf) and the dummy word line DWL are charged to a high potential power supply voltage vcc of, for example, 5V. Here, if the relevant bit line and word line are selected at time t1, the signal BC switches to the level of the low market power supply voltage V,8. Also, word line WL
■. - level, dummy word line control signal DwL
Towards the level of book ha ■ oe, dummy word i DWL
Head towards the level of Hv8°. The waveform diagram in Figure 2A is data “
Since we are talking about reading 0'', for example, if we look at the memory cell (Q+s r Co ), when its node WL goes to the level of ■co* and the transistor Qls turns on, a photoelectric current is applied to the bit line BL. The voltage that was
The charge of cc flows into the capacitor C11.
This is why the value of the bit line BL decreases after a while from time t1 in the figure.

The drop is indicated by ΔVBL.

On the other hand, regarding the dummy cell DC side, since the potential of the dummy warp line ``t'' drops after time t1, the potential of the bit line ``t'' also drops via the capacitor C12.This drop is caused by Δ■ in FIG. 2A. Here, let's make a trial calculation of the above ΔVBL and the ΔVBL. First, let's assume that the bit mochi's answer is 'kcah' (normally BL and t have the same capacitance), and the memory cell capacitor C1□. The capacitance is C8,1, and the capacitance of the capacitor C1+□ in the dummy cell DC is C61□.Normally, it is set to C91□-2CC1.Sense amplifier S
This is to ensure that reading by A+ can proceed smoothly in relation to the reference voltage which will be described shortly. If the amount of charge that the capacitor C1l absorbs from the bit scarlet B L is QCI+, then Qc+ □-r VBL X CCI to Vcc
Cc+ + (1). Therefore, the voltage Δ■1
Hato becomes. Also, regarding the dummy cell DC, the capacitor C1□ is connected to the dummy word line DWL (its voltage is VDW
Q is the amount of charge absorbed from L). 12, Qc+
2”'; Vowt, xCct2=VccxCctz
(3), and therefore, from the above equations (2) and (4), the heavy pressure ΔVn is later amplified by the sense amplifier SA. That is, L
When the E (latch enable) signal (see FIG. 2A) is applied to transistor Q8 of FIG. 1, transistors Qls and C14 of FIG.
! The difference between BL and BL is 11 pressures (shown after time t2 in FIG. 2A above).
~ is done (however, the readout output line is not shown)
. A similar operation is performed when reading data "1", as illustrated in FIG. 2B.Data "1"
08, the capacitor in the memory cell is charged [, (Voo
), there is no charge transfer from ldBLl to capacitor C11, and as shown in FIG. 2B, the potential of bit green BL is ■. It is 11 of 0. In this case, the iBT, , BLO difference voltage can be amplified after time t2 in a state reversed from that in FIG. 2A.

By the way, the problem is that the power supply voltage fluctuation (usually 4.5
7 for 5.5V), the data is always correct.
If it reads ``0'', it means it's in a colander.

FIG. 3 is a waveform diagram used to explain the operation when a power supply voltage fluctuation occurs in the semiconductor memory of FIG. 1, and the reading of the diagram is the same as that of FIGS. 2A and 8. In this waveform diagram, the power supply voltage fluctuation is V, clΔv
oo, especially the power supply voltage V. . ga v,
:cj:t) Δ”cc is shown.

What should be particularly noted here is the increase (the same applies to the case of decrease) Δvo in the power supply voltage Vcc.

On the other hand, the potential of the dummy word line DWL quickly follows and increases by Δ■ce, whereas the potential of the bits aBL and B
The potential of L reacts only extremely slowly (9). Due to this difference in reaction, (BL.

11.) and DWL, a voltage difference of ΔV occurs. Under such conditions, if memory selection (reading of data '0') occurs at time t1, a situation different from that shown in FIG. 2A will occur.
1. BL between, BL' potential and 11-1 in Fig. 3
．． BI3 between. ] If you compare the total potential with '3L', there will be a difference between the two.

By the way, when the potential of the main group 1 of the II I II l"O" discriminator mentioned above approaches that 1 co, the pavi
'0# may be incorrectly determined.

This j, when expressed in full mathematical formulas, ^1f ΔVIIL and Δ
VIIL is shown as follows. The amount of charge QcB flowing into the capacitor ell in the memory cell is Qc+s#VB■, xcC1l=vCCxcC11 (6
), p1ΔvBL becomes. On the other hand, looking at the capacitor Ctt in the dummy cell DC, the amount of charge QC+2 flowing into the dummy word line DwI is as follows: Qo1□=vDwLxCc1□=(vcc+ΔVcc)
×cc l 2 (8), and ΔVBL becomes. Therefore, by comparing equations (7) and (9) above, it can be seen that ΔVBL contains an error of 270 minutes. This error of Δvc0 causes erroneous reading of data. Therefore, the present invention uses some means to ensure that both the potential of the dummy load line DWL and the potential of the bit lines B L and B I fluctuate in exactly the same step as the fluctuation of the power supply voltage. and prevent the generation of the differential voltage ΔV shown in FIG.

FIG. 4 is a waveform diagram used to explain the operation within the semiconductor memory achieved by the present invention, and how to read it is the same as in FIGS. 2A, 2B, and 3. Now, even if the power supply voltage Vco fluctuates stepwise (-1=increase) I- as shown in the figure before the time, as shown in Fig. They will change in exactly the same step.

If this happens, the difference MIFFΔV in Figure 3 will not occur,
Time 1. From now on, the chart is exactly the same as Figure 2A,
The voltage will change. In other words, the potential of the bits (@3L, B) will move on a predetermined chart regardless of the presence or absence of power supply voltage fluctuations.

This means that erroneous reading of data does not occur due to power supply voltage fluctuations.

FIG. 5 is a circuit diagram showing a semiconductor memory according to the present invention which can obtain the operating waveforms shown in FIG. 4. In this figure, components labeled with the same reference symbols as in Figure 1 are the same. Therefore, the configuration of the dummy cell Dσ is a particularly changed part.

In this dummy cell DC', the capacitor temperature is 2°C.
n2, etc. are the same as before, but transistors Qls + Q17 and transistors Qr are added to each capacitor.
L6Qn7 etc. are added, and the dummy word line DW in FIG.
L was removed. In FIG. 4, the dummy word line DWL
This is why it is expressed as DwL/, and the actual potential is equivalent to the potential indicated by that rule. Further, the dummy word line control signal DWL* in FIG. 1 is commonly applied to each gate of the new transistors Q1y+Qn7, etc.

Furthermore, the BC signal in FIG.
It is commonly applied to each y-t such as ls + Qna. Note that the new transistors Q17, Qn7, etc. are substantially equivalent to the transistor Q7 in FIG. In this case, attention must be paid to the functions of the new transistors Qrg + Qn6 and the like.

Conventionally (see Figure 1), capacitor CI 2 + Cn2
The other end (each end is bit line BLl, ■3LnVCMj:
), the power supply voltage V[,
In the present invention, instead of supplying c (see Fig. 5),
The charging voltage of bit line BL++ port Ln is outside. , transistor Q16 r Qn6 ヲB, and these capacitors CI□.

It was decided to supply it to the other end of Cn2. Then, /
-)'Q, (E) potential (conventional dummy word line randomization potential, i.e. DM in Fig. 4, 'equivalent'f)
) is always 'r' of bit line B L H + I' Ln
By moving to follow the position w, the generation of the disadvantageous voltage difference ΔV shown in FIG. 4 is not allowed. Considering this kind of capacitance (parasitic capacitance) and bit line -ni, □1. In the band 5□, the current flowing through the bit line is limited by Qn r Q10 and the capacitance of the bit line is large, so the potential of the bit line changes very slowly. - Since the bit line capacitance is extremely small compared to the bit line capacitance, the node side capacitance l can sufficiently follow very gradual changes in bit line potential. In this way, DWL' of the same step shown in FIG. 4, especially near time t1,
It is possible to realize the voltage transition of BL and BL.

As described above, according to the present invention, a one-transistor dynamic type semiconductor memory is realized that can always read data correctly regardless of power supply voltage fluctuations.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a general one-transistor dynamic type semiconductor memory to which the present invention is applied;
Figures A and 2B are waveform diagrams used to explain the operation of the semiconductor memory shown in Figure 1, and Figure 3 is a waveform diagram used to explain the operation when power supply voltage fluctuations occur in the semiconductor memory shown in Figure 1. 4 is a waveform diagram used to explain the operation in the semiconductor memory achieved by the present invention, and FIG. 5 is a semiconductor memory according to the present invention that can obtain the operation waveforms shown in FIG. 4. It is a circuit diagram showing IJ'Iz. S Al, S A n-sense amplifier, BLl +
BLI ”'Pair of pips) line% BLnl BLn・
...Pair of bit lines, WL...Word line, W line...
Dummy word line, ■ru*...Dummy word control signal, DC, DC'Kasa゛cniYi5''n5...Capacitors and transistors forming memory cells, BC...Bit line charge-up signal.Patent applicant Fujitsu Ltd. Patent Application Agent Ufumido Akimizu Akira Patent Attorney Kazuyuki Nishidate 5P Riju Yukio Uchida Patent Attorney Akira Yamaguchi

Claims (1)

[Claims] 1. A pair of pit lines connected to a sense amplifier, and an iW
A dummy cell comprising a memory cell connected to one of the pair of Nohit lines, a capacitor connected in series to the other of the pair of Nohit lines, : In a one-transistor dynamic type semiconductor memory comprising a word line that selects the memory cell and a bit line charging circuit that charges the # bit line, the dummy cell is connected between both ends of the capacitor. and a second transistor connected in series with the first transistor and grounded, the first transistor is turned on during timing to charge the pair of bit lines to the power supply voltage. A semiconductor memory characterized in that the second transistor is turned on at a timing when a dummy word line control signal corresponding to the word line is sent.