JPH01196791A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To rapidly read the quartered multivalued data without using a stair step signal by connecting a memory cell for every bit line of the first and the second bit line pair of a prescribed capacity and reading the contents of a writing for every bit line pair. CONSTITUTION:The first bit line pair of a bit line BL1 and an anti BL1 and the second bit line pair of a bit line BL2 and an anti BL2 having the capacity of about 1/2 of the 1st bit line pair are connected to the transistors Q9, Q10 of a transfer gate. Dynamic memory cells M1, M2 are respectively connected to the bit line BL1 and the anti BL1 to write the binary data in the quartered value. The writing data of the cells M1 or M2 selected by a word line WL1 or WL2 refers to a reference voltage by a dummy cell D1 or D1' and is read through a sense amplifier SA1 connected to the bit lines BL1, BL2 operating in response to a precharge circuit PRE1. To the memory cells M3, M4 of the bit line BL2, anti BL2, similarly, the stair step signal is not applied to the word line to rapidly read the multivalued data of the quartered value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Industrial Application Field) The present invention relates to a semiconductor memory device, and particularly to a large capacity memory device that can be dynamically and randomly accessed.

(Prior art) Among MO3 type semiconductor memories, especially dynamic type RAM
The capacity of DRAM (DRAM) has been steadily increasing at a rate of four times every three years. Recently, IM bit DRAM has entered the mass production stage, and 4 to 1 bit DRAM will be commercialized soon.

It is thought that the degree of integration of DRAM will increase to 16 Mbits and 64 Mbits in the future. High-precision microfabrication technology is required for higher integration of DRAMs, and new technologies such as grooved capacitors are also required to obtain large capacitor capacitance with a small occupied area.

In order to increase the capacity of DRAM, DRAMs that are not just extensions of current technology but can store multi-bit information in a single memory cell have also been proposed (for example, in 1987, V
SLI Symposium Proceedings p. 49-50). A DRAM using such a multilevel cell is relatively easy to manufacture because it uses an established process technology.

However, a circuit for sensing multilevel cells is generally complicated and access time is also long. For example, if a stepped word line signal is used to read and write information in a multilevel cell, the access time will be several orders of magnitude faster than in a normal DRAM.
It becomes 00 times more.

(Problems to be Solved by the Invention) As described above, DR using multilevel cells that has been proposed in the past
AM has the problem of long access time.

An object of the present invention is to provide a DRAM using a multilevel cell based on a completely new principle, which solves these problems.

[Configuration of the Invention (Means for Solving the Problems) A DRAM according to the present invention includes a first bit line pair and a second bit whose capacity is approximately 1/2 that of the first bit line pair. It has a divided bit line structure in which line pairs are connected via transfer gates.

A plurality of dynamic memory cells each having one of four potentials written into a storage node are connected to each bit line pair. Also number 1. First and second dummy cells are connected to the second bit line pair, respectively. A first reference potential set between the upper two values and the lower two values of the four-valued potentials is written into the dummy cell. First and second sense amplifiers are provided for the first and second bit line pairs, respectively. The first sense amplifier sets the information potential to "H" level or '' with reference to the first reference potential.
The second bit line pair has a second reference potential for discriminating between the upper two values of the four potentials, or a second reference potential for discriminating between the two lower potentials. A third dummy cell is provided in order to obtain a third reference potential for the purpose of Using this reference potential as a basis, the second sense amplifier identifies the upper two values or the lower two values.

(Operation) According to the present invention, 2-bit information expressed in 4 values can be stored in one memory cell by utilizing the divided bit line structure and charge distribution.

The circuit configuration can be realized by simply making minor changes to that of a conventional DRAM, and there is no need to use a stepped signal waveform for word line driving, and a normal word line driving circuit can be used. Since 2-bit information can be read and written with one memory cell, twice the capacity can be obtained with the same number of memory cells as in the past, and the same capacity as in the past can be achieved with a smaller memory chip area.

(Example) The present invention will be explained in detail below.

FIG. 1 shows the main structure of a DRAM according to an embodiment. The bit line pair is a first bit line pair BLI.

BLI and the second bit line pair BL2. Divided into BL2,
These are transfer gates Q 91 Q +.

It has a divided bit line configuration connected by. Here, let the capacities of BLI and BLI be Cal, and BL2.
When the capacity of BL2 is CB2, CIJ□ is approximately C
The capacity is weighted to be 1/2 of BI.

Specifically, assuming the memory cell capacity as C5, CB, +CS
and 08□+CS so that the ratio is 2:1. A first sense amplifier S is connected to the first bit line pair BLI, BLI.
AI and precharge circuit PREI are provided. Second bit line pair BL2. BL2 is provided with a second sense amplifier SA2 and a precharge circuit PRE2. sense amplifier SAI.

An example of the internal configuration of SA2 is shown in FIG. Further, an example of the internal configuration of the precharge circuits PREI and PRE2 is shown in FIG. Both are the same as those commonly used in conventional DRAMs.

A plurality of DRAM memory cells each consisting of a MOS transistor and a MOS capacitor are connected to each bit line pair. In FIG. 1, one memory cell Ml, M2 is shown on each of the first bit line pair BLI, BLI, and one memory cell M3, M4 is shown on each of the second bit line pair BL2, BL2. . As described later, one of four potentials is written into these memory cells. These memory cell capacitors C3°C
-1+... has a capacity of C8. A first dummy cell pair Di is connected to the first bit line pair BLI, BLI.

D2 is connected. This dummy cell Dl.

D2 stores the four-value potential stored in the memory cell, and stores the upper two potentials.
a first reference potential for detecting the value and the lower two values;
In this embodiment, (1/2)Vcc is written. The capacitors CI r of these first dummy cells Di and D2
The capacitance of C2 is also C8, which is the same as the capacitance of the memory cell. Second
A second dummy cell pair D3. D4 and a third dummy cell pair D3', D4' are provided. Second dummy cell D3. D4 is the first
Similarly to the dummy cell pair Di, D2, the first reference potential is written. Third dummy cell pair D3'.

D4' is the second dummy cell D3. The dummy word line DWL2, which is the same as D4, is driven by DWL2, and the total capacitance of capacitors C5 and 07, capacitors C6 and 0
The capacity ratio is set so that the total value of the capacities of C7 and C8 is C8, respectively, as will be explained in detail later. Third dummy cell D3'.

D4' is connected to the second bit line pair BL2. through the Qth MOS transistor, Q12. It is connected to BL2, and at the same time, it is connected to the first bit line pair BLI, BLI via MOS transistors Q25+Q26. This is because the third dummy cells D3', D4' read the information potential read out to the first bit line pair BLI, BLI, and the second dummy cell D3. This is because it is provided for distributing potential between D4 and creating a second or third reference potential as described later.

The first bit line pair BLI, BLI is connected to the transfer gate Q7. Input/output line 110f via Q8.

1101. Second bit line pair BL2.
Similarly, BL2 is connected to input/output lines 1102 and 1102 via transfer gates Q10 and Q20.

The first bit line pair BLI, BLI is further provided with auxiliary dummy cells Di', D2', and the second bit line pair BLI is further provided with auxiliary dummy cells Di', D2'.
L2. Similarly, auxiliary dummy cells D3' and D4 are provided in BL2.
' is provided. These auxiliary dummy cells are used to maintain the capacitance balance of the bit lines.

The operation of the DRAM configured in this way will be described next.

FIGS. 4 to 6 are diagrams for explaining reference potentials during reading, and FIG. 7 is an overall operational waveform diagram. One of four potentials is written into the storage nodes of the memory cells M1, M2, . . . . In this example, OV,
(1/3)Vcc.

(2/3) There are four values of Vcc and VCC. These 4
The value potential corresponds to 2-bit information.

That is, 0■ is (0, O), (1/3), Vcc is (0,
1), (2/3)'Vcc is (1,0), VCC is (1
, 1).

First, during reading, one selected word line is “L”.
# level (e.g. OV) to H” level (e.g. 7V)
stand up. Assume now that the word line WLI in FIG. 1 is selected. At this time, information on storage node N3 of memory cell M1 is transferred to bit line BLI. At this time, as shown in FIG. 7, the clock φT is at the ``H'' level, the transfer gates Qg + Q, o are in the on state, and the read information is transferred not only to the BLI but also to the BL2. At the same time as selecting the memory cell on the bit line BLI, the auxiliary dummy cell D3' provided on the bit line BL2 is simultaneously selected. This is a dummy cell having a built-in capacitance Q Cs.By such selective driving, the capacitance of BLI becomes CB 1+Cs and the capacitance of BE2 becomes cs2+cs.

Note that when the word line that selects the memory cell on the bit line BL2 side rises, □ simultaneously selects the auxiliary dummy cell D1' on the BL1 side. This results in
Again, the bit line capacitance ratio is maintained as described above.

All bit line pairs are connected to precharge circuits PREI, P in advance.
It is precharged to (1/2) Vcc by RE2, and when the word line is selected as described above, the potential obtained on the bit line is according to the four-value potential written in the memory cell. There are four potentials VaLi (
i-1, 2, 3, 4). This potential vBL1 is
More specifically, it is as follows. That is, the potential of memory cell data is set to Vl (Vl-0, V2-(1/3
) Vcc, V3 = (2/3)Vcc.

V4-Vcc), (CD 10Cs) (1/2)Vcc+Cs vi=
(CB +2Cs) V[lLl
- From (1), VBLI - (1/2)Vcc (CB+C5)/
(C8+ 2 Cs)+Vi Cs/(Cs+
2Cs) - (2). However, cB””C1
l l +C[l 2.

Here, (CRI+CS): (C[12+C8) =
As already stated, there is a relationship of 2:L-(3).

A specific numerical example will be given. For example, CS+-250f
F, c, 2-100 f F, C5-50f
If F, (Cn++Cs) : (C[+2+C5) −
300:150=2:1. Then, by substituting these values into equation (2), we get: V Bt, I −2,2222+ 0.1111V j
...(4). Substituting Vl into each equation (3) yields: ■80-2.2222 [V] VBE2-2.4074 [V] VBL3-2.5926 [Vl VBL4-2.7778 [Vl].

Next, the potential of such a bit line is sensed. First, after the data of the memory cell is completely transferred to the bit line as described above, the first bit line pair BLI.

BLI and the second bit line pair BL2. Transfer gate Q91QIO between BLZs is turned off to isolate these bit lines. and the first bit line pair BLI, BLL
The data transmitted to the second bit line pair BL2°BE2 is sensed separately as follows, and finally A/D converted into a 2-bit digital value.

First, the sensing operation is performed on the first bit line pair BLL.

Let's start with the sense of BLI. When the dummy word line DWLI changes from the 'L' level to the 'H' level, the data of the dummy cell D2 is read onto the bit line BLI.

The precharge potential of dummy cell D2 is (1/2)Vcc
Therefore, no potential change occurs on the bit line. At this time, the stray capacitance of BLI of the first bit line pair BLI, BLI is equal to its own capacitance CB1 and memory cell capacitance In C
The sum of s is C81+C5. The stray capacitance of the other bit line BLI is its own capacitance ff1co + and the demi-cell's capacitance fil c s. In other words, the capacity is balanced. Next, the n-channel flip-flop drive signal 5ANI and the p-channel flip-flop drive signal 5API are raised as sense amplifier drive signals.

As a result, the potential of bit line BLI becomes VBLI or V
In the case of BL2, that is, when it is one of the lower two values among the four values, the potential of BLI is (1/2) Vcc, so BLI goes to 0 [Vl, BE, 1 goes to 5 [Vl]. Each is amplified. When the potential of BLI is either the upper two values VBL3 or VLIL-1, BL1 is 5[
Vl and BLl are respectively amplified to 0[v]. This situation is shown in FIG.

After the sensing on the first bit line pair BLI, BLI is completed, the data is transferred to the third dummy cells D3', D4'. That is, the clock φT is set to "H" level and the transfer gate Q2. .

Turn on Q26 and transfer the data of BLl to dummy cell D4.
' Transfer the BLI data to the node N6 of the dummy cell D3.
' are respectively written to node N5. For example, BLI is V
. If 0, node N5 goes to VCC and BLI goes to 0 [■
], node N5 becomes 0 [v]. Node N6
is opposite to node N5. After this, transfer gate Q2. .

Q26 is turned off.

In this way, after writing the data on the first bit line pair BLI, BLI into the third dummy cells D3', D4',
bit line pair BL2. Let's move on to the sensing operation in BL2. In the sensing operation here, the "H" level which is the sensing result on the first bit lines BLL and BLI is vs. L3 and VB.
It is determined whether the "L" level is VBL1 or VBL2. For this purpose, third dummy cells D3', D4' are used, and second dummy cells D3. By mixing and reading the signal charges of D4, the reference potential V between v8L l and VBL2
A reference potential VItEFH between REFLs or VBL3 and VBL4 is created. For this purpose, a second dummy cell D3. It is necessary that the capacitances of the capacitors C7 to C8 of D4 and the capacitances of the capacitors C, 5, and Co of the third dummy cells D3' and D4' are set to satisfy a certain relationship.

Specifically, it is as follows. Second dummy cell D3. D
4 as VCs, and the third dummy cells D3' and D4
Let the capacity of ' be xC3. However, x+y-1. Second dummy cell D3. As mentioned above, D4 has (1/2)
Vcc is written, and 0, which is the result on the first bit line pair BLI and BLI, is written into the third dummy cells D3' and D4'.
[V] or VCC is written. Therefore, the second dummy cell D3 and the third dummy cell D3' are connected to the bit line B at the same time.
When the second dummy cell D4 and the third dummy cell D4' are simultaneously read to the bit line BL2, the following relationship is obtained.

x Cs ・0 +y Cs (L/2)Vcc-Cs
VL...(5) x Cs -Vcc+Y Cs (1/2)Vcc
-C9VH (6) Here, vL and VH are average potentials written in the second dummy cell and the third dummy cell. Second bit line pair BL2. To sense BL2, set the reference potential VREFH+VREFL as shown in FIG.
As shown in FIG. 6, V Rgp++-(V BL3
+VBL4)/2VREFll-(VB
Most preferably, LI + VBL2)/2. At this time, the following formula holds true.

C82(1/2)V cc+ Cs V H= (C
B2+Cs) (L/2) (VBL3 +VBL4
)...(7) CB2(1/2)V cc+ Cs V L= (
CB2+C5) (1/2) (VBLI +VB
L2)...(8) From these, Vll +VL = Vcc -
There is the following relationship (9). Also, from equations (5) and (6), VHVL-XC8-(10) (7) and (8), Cs (Vu V+,) - (Ca 2 + Cs ) (1/2) f (
VB L 3 + VB L 4 ) −(Vnt
I” VBL 2 ) 1...(11) C8 (VHVL) = (2/3) (CB2+ Cs ) Cs Vcc/
(CB + 2 C3)...(12) Here, from formula (3), (C112+ Cs) / (Co + 2 Cs
) = (CB2+ C9)/f(Cn++ C3)
+ (CB2+ Cs)]=α/(2α+α) −1
/3 holds true. However, α is a constant.

Therefore, from formula (lO), it becomes X-2/9...(14), and y-7/9...(15)
becomes.

From the above, the bit line capacitance icB, C8□, and cell capacitance C
8, the second dummy cell D3. The capacitance of capacitors C7 and C8 of D4 is set to (2/9)Cs, and the capacitance of capacitor C5 of third dummy cell D3' and D4' is set to (2/9)Cs.
, C6 is set to (7/9)Cs.

Therefore, the dummy word line DWL2 connects the second dummy cell D4. When the information of the third dummy cell D4' is transmitted to the second bit line BL2, the first bit lines BLI, BLL(
7) The potential is distorted 5 [Vl.

0 [Vl, the potential of this second bit line BL2 is the higher reference potential V It E shown in FIG.
It becomes FH. As a result, if the potential of the second bit line BL2 is V13L3, the potential of the second bit line BL2 becomes 0 [Vl by driving the sense amplifier SA2, and the potential of the other second bit line BL2 becomes V13L3. are amplified to 5 [Vl, respectively.

If the potential of the second bit line BL2 is VBL4, the potential of BL2 is amplified to 5[Vlr] and the potential of BL2 is amplified to 0[Vl], contrary to the above, by driving the sense amplifier SA2. This situation is as shown in FIG. First bit line BLI, BLM7) Potential cutoff, O[Vl.

5[Vl, the potential of the second bit line BL2 becomes the lower reference potential vnEFL shown in FIG. As a result, if the potential of the second bit line Bt2 is VB=1, the potential of the second bit line BL2 becomes 0 [Vl by driving the sense amplifier SA2, and the potential of the other second bit line BL2 The potentials of are each amplified to 5 [■].

If the potential of the second bit line BL2 is VBL2, the potential of BL2 is amplified to 5[Vl] and the potential of BL2 is amplified to 0[V] by driving the sense amplifier SA2, contrary to the above. This situation is as shown in FIG.

As a result of the above, the potential after reading becomes VBLI(-2,222
2 [Vl ), the potentials of BLI and BL2 are both 0.
[v], Vo L 2 (-2,4074[Vl
), then BLI is 0[Vl, BL2 is 5[Vl, Vs L 3 (-2,5926EV]), then the potentials of BLI and BL2 are both 5[Vl, Vo L
4 (-2,7778[Vl), then BLI
is amplified to 5 [Vl and BL2 is amplified to 0 [Vl, respectively. In other words, if the data in the memory cell is Vl-0[Vl, both the data from the process 101 and l102 are 0[Vl is V2-
(1/3) Vcc, from l10f to 0 [Vl
, l102 to 5[v] is Vl-(2/3)Vcc, l101 to 5 [Vl, l102 color 0
[If ¥ko is V4-VCC, l101 and l10
Both 5 [Vl are output from 2. In other words, the 4-value potential written in one memory cell is converted into 2-bit digital information and output.

Next, a method for writing external 2-bit data into a memory cell as 4-value data will be explained.

(1)! 101. Let l102 be both 5 [■] (
1, 1) At this time, the first bit line BLI and the second bit line BL2 are each sense amplifier SAI.

SA2 senses 5 [Vl. The capacitance of the first bit line BLI and the capacitance of the second bit line BL2 are set to approximately 2/1 as described above. ((4) above)
formula). sense amplifier SAI.

When the sensing operation of SA2 is completed, the sense amplifier n-channel side activation signals 5ANI and 5AN2 are changed from the "L° level to an intermediate level (for example, 2.5[Vl]),
In addition, the p-channel side activation signals 5API and 5AP2 are “
H'' level to an intermediate level. As a result, bit lines BLI and BL2 become floating. After that, when transfer gate Q9.Q[ is turned on, BL
I and BL2 are shorted together and become 5 [Vl, and BLI and B
L2 is short-circuited and both become 0 [■].

Then, by closing the word line of the memory cell to which data is to be written, 5 [Vl, ie, data (1, 1), is stored in that memory cell. This situation is shown in FIG.

(2) l101 as Vc c =5 [V],
When writing (1, 0) with I102 set to 0 [■], the first bit line BLI is set to 5 [V] by the sense amplifier SAI, and the second bit line BL2 is set to 0 by SA2.
[V] is sensed respectively. When the sense amplifier is deactivated after sensing ends, the bit lines BLI and BL2 become floating. After that, transfer game) Q9.
B+.

When turned on, BLl and BL2 are short-circuited and their potential is determined by the following formula: (CB1+ cs) HVCC/(CB"2 C5)"
(CB2+ C5) ・0/(CB”2 C5)=
(2/3) Vcc-3,333 [Vco. On the other hand, for BLL and BL2, (1/3) Vc c =1. QQ7 becomes [V]. Thereafter, by closing the word line of the memory cell to be written, (2/3)Vcc1, that is, data (1, 0) is stored in that memory cell. This situation is shown in FIG.

(3) l101 to Vcc-0 [V co
, When writing (0, 1) with l102 at 5 [V], the first bit line BLI is connected to the sense amplifier S
The second bit line BL2 is set to 0 [V] by AI, and the second bit line BL2 is set to SA2.
are sensed at 5 [V] by each. When the sense amplifier is deactivated after sensing, the bit lines BLI and BL
2 becomes floating. After that, transfer gate Q9. B+.

When turned on, BLl and BL2 are short-circuited and their potential is determined by the following formula: (C1, I+ 0Cs) ・0/(CB+2 C5)"
(CB2+ C3) ・Vcc/(Cs+2 C5)-
(1/3) Vcc-1,0G7 [V]. On the other hand, for BLL and BL2, (2/3)Vcc = 3.333 [Vco. Thereafter, by closing the word line of the memory cell to be written, (1/3)Vcc-, that is, data (0, 1) is stored in that memory cell. This situation is shown in FIG.

(4) l101. When writing (0, O) with both l102 set to 1:0 [V], the first bit line BLI and the second bit line BL2 are each connected to the sense amplifier SAI.

It is sensed to 0[v] by SA2. After the sense ends,
Sense amplifiers SAI and SA2 are deactivated. As a result, bit lines BLl and BL2 become floating.

After that, transfer gate Q9. When B+o is turned on, BLI and BL2 are shorted and both become 0 [V],
BLI and BL2 are short-circuited and both become 5 [V]. Thereafter, by closing the word line of the memory cell to which data is to be written, 0[v], that is, data (0, 0), is stored in that memory cell. This situation is shown in FIG.

As described above, according to this embodiment, a large-capacity DRAM that stores 2-bit digital information in one memory cell and can be randomly accessed is realized.

The process technology is the same as that of conventional DRAMs, and the degree of integration can be substantially doubled compared to conventional DRAMs, which is extremely advantageous in practical terms. Furthermore, since it is writable, it is naturally possible to refresh it, and it can be controlled in the same manner as conventional DRAMs, making it easy for users to use. Furthermore, compared to conventionally proposed multi-level cells, there is no need to use step-like signals to drive word lines, and high-speed performance several hundred times faster can be achieved. The access time is slower than that of an in-shell 1 bit/cell DRAM due to the need to perform two sense operations in one active cycle, but it is only two to three times as slow at most.

The present invention is not limited to the above embodiments.

For example, in the embodiment, the capacitances of the first bit line pair and the second bit line pair are set to be 2/1 when - number of memory cells are connected to each of them. As is clear from the description of the embodiment, this is to obtain four-value storage potential equally divided by this capacitance ratio. However, the four-value storage potentials do not necessarily have to be equally divided, and therefore the capacitance ratio of the bit lines does not have to be set strictly as in the embodiment. Similarly, the capacitor capacitance ratio between the dummy cell of ff12 and the third dummy cell is not limited to the values in the example, as long as a necessary reference potential can be obtained.

The pond water invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, it is possible to store 2-bit information in one memory cell with 4-value potentials, and also to store 2-bit information in 4-value potentials without using a stepped waveform for the word line drive signal. A DRAM capable of sensing potential can be obtained. Further, according to the present invention, it is possible to increase the capacity of a DRAM without changing conventional process technology.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the main part configuration of a DRAM according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of the sense amplifier, and FIG.
The figure also shows a configuration example of the precharge circuit, FIG. 4 is a diagram for explaining the sensing operation by the first bit line pair, and FIGS. 5 and 6 show the sensing operation by the second bit line pair. FIG. 7 is a waveform diagram showing the flow of the entire sensing operation, and FIGS. 8 to 11 are diagrams explaining the data writing operation. BLI, BLI...first bit line pair, BL2°BL
2... second bit line pair, Ml, M2. M3゜M4・
...Memory cell, Di, D2...First dummy cell, D3. D4... second dummy cell, D3'. D4'...Third dummy cell, Di', D2'. D3', D4'... Auxiliary dummy cells, WLI. WL2, WL3, WL4...word line, DWLI
. line, SAI...first sense amplifier, PREI...
・First precharge circuit, SA2...Second sense amplifier, PRE2...Second precharge circuit, Applicant's representative Patent attorney Takehiko Suzue Konichi〇- Figure 3 Li Li Time Figure 8 Figure 9 Figure 10 Bamboo ++ Ct I

Claims (1)

[Claims] A plurality of dynamic memory cells in which one of four-valued potentials is written to a storage node, and a first reference potential set to an intermediate value between the upper two values and the lower two values of the four-valued potentials are written. A first bit line pair to which a first dummy cell pair is connected, a plurality of dynamic memory cells to which one of the four potentials is written to the storage node, and a first bit line pair to which the first reference potential is written. Selectively connect the first bit line pair and the second bit line pair to a second bit line pair to which two dummy cell pairs are connected and whose capacity is approximately 1/2 that of the first bit line pair. a transfer gate connected to a first bit line pair to transfer the information potential of the memory cell to the first bit line pair;
A first sense amplifier detects information by distributing it to "H" level and "L" level using a reference potential of the memory cell, and is connected to a second bit line pair and turns on the transfer gate to turn on the information potential of the memory cell. is distributed to the first and second bit line pair, and the "H" level and "
A second sense amplifier that performs information detection by distributing to the L'' level and the second dummy cell pair are selectively driven simultaneously and connected to the second bit line to obtain the second or third reference potential. A semiconductor memory device comprising a third dummy cell pair.