JPS5857691A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To increase the switching speed, by forming a pinch resistance at an emitter of a transistor of a bias circuit and keeping the discharge current at a constant level regardless of the fluctuation of the transistor adverse beta. CONSTITUTION:A bias circuit BS absorbs the discharge current frorm a memory cell MC along with transistors T44 and T'44. A pinch resistance uses the base layer formed right under the emitter, and the resistance value depends on the width of the base layer. A pinch resistance RP is formed at the area of an emitter diffused resistance R2 of a transistor T42. The value of the pinch resistance increases when the adverse beta and the shunt component of the discharge current to a non-selected bit line are large. Thus the discharge current increases automatically.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memories, and particularly to semiconductor memories using saturated memory cells.

A semiconductor memory consists of a large number of word lines, a large number of bi) lines, and a large number of memory cells arranged at each intersection of these lines. Various types of memory cells have been proposed, and for example, saturated memory cells are also widely used.

The present invention refers to a semiconductor memory that utilizes this saturated type memory cell.

By the way, in semiconductor memory, the read 1""O1
In order to hold the data for one period, a so-called one-period current is applied to the memory cell. Then, when a word line changes from selected to non-selected, its holding current is discharged. Therefore, the larger the bed wake flow, the faster the switching speed when switching the selection. However, since it is preferable that the C1 holding current (1, .) be as small as possible in order to increase the number of semiconductor memories and to reduce power consumption, it becomes impossible to achieve the switching speed of the crystal speed. Therefore, the present applicant has made it possible to selectively draw in the release: IL city flow (■D) to the selected word line,
A proposal has already been made to increase the switching speed by this method.On the other hand, in a saturation type memory cell, the emitter of a detection transistor in a half-selected memory cell is raised to a high potential. This is to prevent erroneous writing to the half-selected memory cell. Then, a phenomenon occurs in which a part of the discharge current (I, > of the word line is shunted to the unselected bit line), resulting in the inconvenience that the switching speed is not increased that much even though the discharge current (Io) is introduced. arise.

SUMMARY OF THE INVENTION Therefore, an object of the invention is to solve the above-mentioned disadvantages and to propose a semiconductor memory capable of increasing switching speed.

In accordance with the above object, the present invention focuses on the fact that the above-mentioned partial branching of the discharge current (Io) to the detection transistor depends on the inverse β of the detection transistor, and the inverse β can be set virtually unchanged. The present invention is characterized in that a means is introduced to maintain the discharge current (Io) constant regardless of fluctuations in the inverse β.The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a part of a semiconductor memory to which the present invention is applied. In this figure, (3) the memory cell MC is sandwiched between them. In addition, these words @W
,,W-, there are many more memory cells MC. Memory cells M and C also each have a pair of bit lines B, T, .
By selecting one bit line pair and one word line pair, a desired one memory cell can be accessed. Each memory cell reads data of 111 or θ', and the current to hold it, that is, hold'
l! A leg holding current source SIH is provided for drawing in the i current IN. Therefore, when word line switching is performed, the charges on the selected word lines W+, W- are held as 1!
The discharge occurs in the form of absorption of the current IH.

Therefore, the larger the holding current 111 is, the faster the word line switching speed becomes. However, in order to increase the capacity of a semiconductor memory and to reduce power consumption, the smaller the retention IH, the better, which goes against the increase in the switching speed.

Therefore, the present applicant has already proposed a discharge circuit 1)C that can selectively absorb the discharge current fD only for the selected word line 4).

Here, SI,, SI,; is a differential type constant release flow source. Thus, the emission of the bottom cylinder from the word line or (I
, +f,) to achieve rapid switching speed.

Meanwhile, a p-bit clamp circuit has been proposed. This is BCL in the figure. When the internal transistor pair of the pictoclamp circuit BCL is turned on, the detection transistor (T in the selected memory cell on the left side in the figure) in the half-selected memory cell Me (the memory cell on the right side in the figure), The emitter of 'I'2 (same as 'I'2) is raised to a high potential to prevent erroneous writing associated with writing to a selected memory cell.

All of the above are publicly known matters.

Next, let's consider the memory cell MC a little more. N
FIG. 2 is an enlarged view showing one of the semiconductor memory cells MC in FIG. 1. This figure Nioite IJL,
B h, W+, W-, Tl l"'2'J
As already mentioned, the detection transistors T, '11□ are made up of multi-emitter transistors. Also, T and T4 are PNP type load transistors. It surrounded the
Indicates that it is in the on state. This memory cell MC
When the word line W is in the non-selected direction.

The charge on W- will be absorbed as a current (IH+Io). Here, the detection transistor, for example 11. If the emitter connected to the bit line 13L (il-Es) is connected to the bit line 13L, and the emitter connected to the word d4- is E, then in a semiconductor memory using a saturated memory cell, the potential of the emitter BS is When the voltage becomes higher than the voltage of the emitter EH, the emitter LUS starts to work as the collector of the inverse transistor, and current flows from the bit line BL to the emitter EH.The potential of the emitter ES becomes higher than the potential of the emitter EH. Regarding this, the pictoclamp circuit BCL (first
It is clear from Figure). The t current flowing from the bit 1513L to the emitter E6 is shown as a dotted arrow i in the figure, but due to this 50% flow of it, the current (IH+ID) that should flow from the word line W- is A part of it will flow to the bit line BL. This means that the presence of the current i inhibits the discharge of charges that should be extracted from each node in the memory cell MC (from selection to non-selection). Thus, the word line discharge current■.

This results in the phenomenon described above in which a portion of the current is shunted to unselected bit lines. Here, when looking at the rate at which the current is shunted to the bit line 81°, it is related to the β (poor current amplification) of the detection transistor T1 as the reverse transistor described above, that is, the inverse β. The larger the inverse β is, the more the current is shunted to the bit line BL. Therefore, the larger the inverse β, the lower the switching speed. Note that the inverse β is in a proportional relationship with the normal β. The current shunting to the pin line HL occurs in the memory cell Me where the potential of the emitter gs is higher than the potential of the emitter. In other words, this applies to all half-selected memory cells whose bit clamp circuits BCL are active. Then, except for one memory cell selected for one selected word (7) word line, the majority of all other memory cells exhibit the above-mentioned value of 6+1, and the value becomes unshieldably large. Semiconductor memories produced from manufacturing lots with a particularly large inverse β suffer from the aforementioned shunting problem, and must be discarded due to manufacturing standards. Then, conversely, it is also possible to think of changing the manufacturing loft in a way that makes the inverse β extremely small. In this case, the centering of the half-selected memory cell will be good and the switching speed will be high. However, reducing the inverse β is undesirable because it increases the load on the word line.

As shown above, even if the inverse β is inconvenient whether it is large or small, it is impossible to guarantee the optimal inverse β for all surface manufacturing rods due to the variation in da. It is Noh. Therefore, focusing on the fact that the magnitude of the shunt depends on the magnitude of the inverse β, we will consider creating a method that can make the inverse β virtually unchanged no matter how the inverse β fluctuates.

Specifically, according to the inverse β for each manufacturing loft, the above (8) Discharge current of constant emission current source SID■. change the directness of

In other words, for a manufacturing loft with a large inverse β, its radiation ``a!''
The value of the electric current 1o is made large so that charges from each node in the semiconductor memory cell can be quickly absorbed.

FIG. 3 is a circuit diagram showing an embodiment of a semiconductor memory according to the present invention. However, only the necessary parts are extracted and drawn. Among the nine constituent elements in this figure, those labeled with the same reference symbols as in FIG. 1 are the same. Then,
The bias circuit BS in the figure is particularly noteworthy.

However, this bias circuit H81j) transistor T44
+ '1' Together with 44, it constitutes a part of the constant discharge spiral flow sources SID and SIQ in FIG. 2 in this figure, the bias circuit voltage vB is the transistor T4. For the base-emitter voltage v8EI, O R2+ 1 (,3R2 Va= 3 'VaEi=+H+1.) is determined by the following equation (1)
VaE+ (1) However, 几2. R3 is the resistance value of the resistors indicated by O and O in the diagram. Also, let go
The flow I is determined by the following equation (2).

VBE4 is the base-to-emitter voltage of transistor T44, and 1L4 is the resistance value of resistor 2. The transistor Illo that flows the discharge current D is a transistor that is turned on only for the selected word line, and together with the capacitor C and the resistor 1t, a switch with a time constant = i
It functions to form f and to absorb all of the T specific current ID for as long as possible. However, these TD, C, R
etc. are not the honzuke of the present invention.

Cocoa, upper Re (1) Oyohi (2) formula no VBEI to V
8E4 Assuming that both are equal to pigeon (which is often the case in IC tips), the following equation (3) holds true.

According to equation (3), in order to change the magnitude of the first discharge flow ID in accordance with the magnitude of the inverse β, since VIIE is constant, the resistances 0, 0, . ■Resistance 1lIIR2, H, 3
.

This means that any one or more of the filters 4 may be made variable. It would be extremely convenient if such a variable operation could be performed automatically according to the inverse β. For this reason, the present invention focuses on pinch resistance. The pinch resistor is a resistor that uses a base layer directly under the emitter, and its resistance value 1tP depends on the width of the base layer. In FIG. 3, the pinch resistor O corresponds to this, and the transistor T4
It is formed in the part of the emitter diffused resistor O of No. 2. The way it is formed can be independent of O, or it can be formed in parallel with @ (
The figure shows an example of the latter).

Now, considering the unique characteristics of pinch resistance 0,
A certain relationship is found. FIGS. 4(A) and 4(B) are graphs schematically showing the custom-made pinch resistance of solid M;
5) shows the relationship between the base width d and the inverse β, however, ○ graph (A) shows the relationship between the base width d and the resistance value P, (
Comparing the two, it can be seen that no matter how the base width d changes depending on the manufacturing lot, the inverse β and the resistance value P change proportionally at roughly the same step. Applying this property, the above formula (3) can be replaced with the formula (11) % formula % (4). 1t3.几4. Since vBE is a constant term, it can be divided into When the above-mentioned shunt flow is large in a dog, the pinch resistance value It J! also increases, and the release flow automatically increases according to equation (4). achieved.

As explained above, according to the present invention, a semiconductor memory is realized which can always maintain a high switching speed ft regardless of variations in production size and soot (variations in inverse β).

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a part of a semiconductor memory to which the present invention is applied, and FIG. 2 is an enlarged view showing one of the semiconductor memory cells MC in FIG.
ffl&m A circuit diagram showing an embodiment of a four-body memory based on the present invention, FIG. , W-...Word line, BL, L
(L・=−・Bit line, MC・・・Memory cell,
q+, , T2...Detection transistor, S1
8. sI meter... Constant current source, BS...
Bias circuit, pinch resistance, Io...
...family 14. Current, ■H...Holding current, VB
...Bias voltage. Patent Applicant Fujitsu Limited Patent Attorney Akira Aoki Patent Attorney Kazuyuki Nishidate 1) Graduated Male Patent Attorney Akira Yamaguchi Figure 2 Figure 4 (△) (B) d-II- d
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Claims (1)

[Claims] 1. A plurality of word lines, a number of bit lines, a memory cell arranged at each intersection of these word lines and bit lines, and a constant current source for absorbing discharge current from the memory cell. and a bias circuit for generating a bias voltage for generating a predetermined discharge 'cardiac current through a predetermined resistance. A semiconductor memory characterized in that a pinch resistor is formed in an emitter portion of a transistor, and the magnitude of the discharge current is determined depending on the magnitude of the resistance value of the pinch resistor.