JPS60217588A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent malfunction of memory and to shorten the access time by providing a circuit for latching a complementary data signal from a memory cell in a read circuit. CONSTITUTION:A circuit 11 for latching readout data by a read circuit 1 having a transistor, which comprises a current switch circuit together with a transistor in a memory cell MC, is added. Although higher node levels in a memory cell previously selected and that selected this time drop simultaneously below a read reference voltage, previous data is provisionally stored in the circuit 1 by setting a double selection margin; therefore, when the same binary data is continuously read out, currents cannot flow simultaneously to a pair of common digit lines CD from a level shift resistance in the circuit 1. Thus switching noises can be removed from an output waveform and the access time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit technology and a technology that is particularly effective when applied to a read circuit of a semiconductor memory device, for example, a technology that is effective when applied to a read circuit of a bipolar static RAM. related to technology.

[Background Art] A circuit as shown in FIG. 1, for example, was developed by the present inventors as a read/output circuit in a bipolar static RAM (random access memory).

That is, a pair of complementary digins 1 to 1 are connected to memory cells MC each consisting of a flip-flop.

D, respectively, and have a reference voltage Vref at the base.
, transistors Q3 . Q-i and this transistor Q
3. A resistor R1° transistor Q5 and a resistor R2 are connected in series between the collector of Q4 and the power supply voltage Vcc.
The read circuit 1 is constituted by the transistor Q6 and a constant current source 11tI2 connected to the emitters of the transistors Qs and Qa.

Transistor Q5 configuring this readout circuit 1.
The collector voltage of Q6 is the emitter follower output transistor Q? , Q8, the data is transmitted to the output circuit 2 composed of a differential ECL circuit, and the data read from the memory cell Me is differentially amplified and outputted to the outside from the output terminal Dout. has been done.

In the above configuration, when the word line W is raised to a select level by a word line driver (not shown) during data reading, the node n1yn2 in the memory cell MC is raised, and the node n1
Alternatively, one of R2 is set to a level V c 1 higher than the read reference voltage V r e f applied to the bases of transistors Q3=Q4, and the other is set to a level V c □ lower than Vref. As a result, a current flows from within the memory cell in the digit line (D or 10,000) on the side of transistor Q1 or Q2, whose base is connected to the Vcl node, and Vcl is applied to the base.

. In the digit line on the transistor Q1 or Q2 side to which the node of D
It is drawn by a constant current source I3+I4 which is provided in common to both.

Therefore, the resistor R7 or R constituting the readout circuit 1
A relatively large current is passed through only one of the terminals 2, causing a voltage drop, which is differentially amplified by the output circuit 2, so that read data is output from the output terminal Dout.

However, in the read/output circuit configured as above, the level Vx of a certain word line falls from the selected level to the non-selected level, and the other word line rises from the non-selected level to the selected level. If, for example, the newly selected memory cell belongs to the same digit line as the previously selected memory cell and has the same binary data written to it, then the previously selected memory cell and the next selected memory cell are Current may temporarily flow from both memory cells. However, when current flows from two memory cells at the same time like this, the digit line is drawn by a constant current source, so the current flowing becomes half of the normal value, reducing the memory cell retention amplitude and causing the selected A dangerous situation arises in which information in the memory cells is destroyed.

Therefore, by setting a condition called address double selection margin that prevents the higher level V c 1 of node n1 or R2 in each memory cell from becoming higher than the reference voltage ref at the same time, as described above, This avoided a dangerous situation where current would flow from two memory cells at the same time.

However, if the address double selection margin is secured in this way, the higher side level V of the node nl+n2 in the previously selected memory cell and the next selected memory cell
A situation occurs in which c1 is also lower than the reference voltage Vrefk at the same time. Then, the transistor Q3 . connected to the digit line D selected at this time. Both Q4 are turned on, current flows from both, and a voltage drop occurs across both resistors R1 and R2 in the readout circuit 1. As a result, the output waveform in the output circuit 2 drops to an intermediate level for a certain period of time as shown in FIG. 2, causing switching noise. As a result, the inventor has revealed that there is a problem in that the memory access time is delayed by the amount of switching noise.

[Object of the Invention] An object of the present invention is to provide a high-speed static RAM that prevents memory malfunction and has a short access time.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, the present invention adds a function of latching read data to a read circuit having a transistor that constitutes a current switch circuit together with a transistor in a memory cell. Even if the level of the high-side node in the memory cell selected to 1 and the memory cell selected next simultaneously becomes lower than the read reference voltage, the previous data is temporarily retained in the read circuit. , when the same binary data is read out continuously, level shift 1 in the readout circuit prevents current from flowing from the resistor to the pair of common digit lines at the same time, thereby removing switching noise from the output waveform and accessing. This achieves the above objective of shortening the time.

Embodiment FIG. 3 shows an embodiment in which the present invention is applied to a bipolar static RAM.

The memory array 3 is constructed by arranging memory cells in a matrix having the same configuration as the flip-flop memory cell MC1 whose configuration is representatively shown. Each memory cell MC1... is connected to a word line W, a current standby line IST, and a pair of complementary digit lines D, respectively.
By constantly pulling T with a constant current source Ia, a current is caused to flow through one path of the flip-flops constituting the memory cell MC1 . . . and information is retained.

One of the word lines W corresponding to the address Ax is selected by a word line drive circuit 5 driven by a selection signal φX output from an X decoder 4 that decodes an X-system address signal Ax supplied from the outside. level (high level). When word line W is raised to the selection level, node n in memory cell MC
, and n2 levels are respectively raised, one being a level V c 1 higher than the read reference voltage V r e f
and the other is set to a level VcO slightly lower than V r e f.

For each complementary digit line pair, D is connected to a common line via Y switch transistors Qy, Qy;
A Y-switching circuit 7 driven by a selection signal φy output from a Y-decoder 6 that decodes a Y-series address signal Ay decodes a Y-switch transistor Q y + Q on any pair of digit lines corresponding to the address AV.
y is turned on. As a result, a pair of digit lines D are drawn by the constant current source 13+I4.

Each of the complementary digit lines D is connected to a transistor Q3. Q4 are connected to each other, and this transistor Q
3. The collector of Q4 is connected to a readout circuit 1 having a latch circuit via common digit lines CD and CD. The output of readout circuit l is connected to emitter follower output transistor Q7. similar to that of FIG. The signal is supplied via Q10 to an output circuit 2 consisting of a differential ECL circuit.

The readout circuit 1 includes, but is not particularly limited to, a latch circuit 11 consisting of a flip-flop connected to a common digit line CD, a diode Dir resistor R□ connected between a power supply voltage ■cc - VEE, and a constant As in the circuit 12a, a diode D2. The level shift circuit 12b includes a resistor R2 and a constant current source I2. and,
The common logic lines CD and CD are connected to the connection node n:3+n4 between the resistor R1 or lR2 in the level shift circuit 12a or 12b and the constant current source ■1 or ■2, and the level of the node n3+n4 is set to the emitter level. Follower output transistor Q? , is supplied to the base of Q8. Note that constant current source work 1 and work 2 are connected to node n
This is to output a level shift voltage when I3 or n4 is set to high level, and is a constant current source I3tI.
Compared to 4, the current flowing is less than half.

On the other hand, the latch circuit 11 has a configuration similar to that of a known flip-flop type memory cell, and includes a resistor R3°R4, transistors Q41, Qs2, and a transistor Q1s+, which constitute a pair of inverters.
Transistor Ql 3 y Q14 for applying positive feedback to the base of Q12 and transistor Q111
A constant current source I5 is commonly connected to the emitter of Q12.

Next, the operation of the circuit of the above embodiment will be explained.

Now, assume that the node n1 in the memory cell MC1 in FIG. 3 is set to a low level V co and the node n2 is set to a high level V c 1.

In this state, the word line W is raised to the selection level,
Assume that the switch transistors Q y r Q y on the complementary digit line pair D are turned on.

Then, the levels VCO and Vcl at the node n1tn2 are raised, and V c 1 is applied to the transistors Q3 and Q4.
The read reference voltage V r e applied to the base of
f, and V c □ becomes slightly lower than V r e f.

Therefore, on the digit line side, the 1-transistor Q in the memory cell whose base potential is high because it is drawn by the constant current source I3.
, and on the digit greenstone side, a current flows out from the transistor Q4, which is drawn by the constant current source I4 and to which a reference voltage V r e f having a higher level than V c □ is applied. by this.

Level shift circuit 12b rather than level shift circuit 12a
Since a large current is passed toward the resistor R1, the voltage drop across the resistor 2 becomes larger than that across the resistor R1, and the voltage drop across the resistor R1 becomes larger than that across the resistor R1.
3 is set to high level, and node n4 is set to low level. This level difference is supplied to the differential output circuit 2 via the emitter follower, thereby being amplified and output. Note that at this time, within the latch circuit ll, the node n6
is set to low level, and node n6 is set to high level.

Next, when a memory cell on the same or another complementary digit (not shown) connected to the common digit lines CD and CD is selected, data different from that of the memory cell selected immediately before is written in this memory cell. Suppose that In other words, in the next selected memory cell, node n1
is set to a high level Vc1, and node n2 is set to a low level Vc1.
c(, then the reference voltage V
The state changes such that a current flows from the transistor Q3 to which e f is applied, and on the digit line side, a current flows from the transistor Q2 in the selected memory cell.

Therefore, in the readout circuit 1, first, the current flowing through the level shift 1-circuit 1.2b decreases, and the level of the node n4 increases. As a result, the base potential of the transistor Q12 becomes high, the collector current increases, and the level of the node n6 in the latch circuit 11 changes from high level to low level due to the voltage drop across the resistor R4. Then, the base potential of the 1-transistor Q11 is lowered, the collector current is decreased, the level of the node n5 is increased, and the base potential of the transistor Q13 is increased. Therefore, the base potential of the transistor Q1□, which is one step lower than the base potential of the transistor Q13, also rises, and the collector current of the transistor Q12 is further increased. By applying positive feedback in this way, nodes n3 and R6
The level of node n4 and Tl
The level of 5 is quickly changed to high level,
Fixed.

On the other hand, when another memory cell on the same or another digit 1- line connected to the common digit lines CD and CD is selected, the same data as the memory cell selected immediately before is written in this memory cell. Suppose that Then, when the word line of the previously selected memory cell falls and the level V c 1 of the internal node n2 becomes lower than the read reference voltage V r e f , the second As shown in the figure, the level V c 1 in the next selected memory cell is set to the reference voltage V r
Since there is a period in which e f does not reach, on the common digit line CD side, the current flowing from the previously selected memory cell changes to a state where it flows from the next selected memory cell. , temporarily the reference voltage V
Current begins to flow from the transistor Q3 to which r e f is applied.

At this time, in the circuit of FIG. 1, the noise shown in FIG. 2 was added to the output waveform due to the current flowing from the transistor Q3, but according to this embodiment, the noise is temporarily read out through the transistor Q3. Even if current flows from within the circuit 1, this current is supplied exclusively from the emitter of the transistor Q14 in the latch circuit 11, which is turned on.

Therefore, the current flowing through the level shift circuit 12a hardly changes, and the levels of nodes n3 and n4, which conventionally fluctuated as shown in FIG. 4(A), change to the level shown in FIG. 4(B).
It becomes constant as follows. This prevents the bases of the two transistors constituting the current switch of the output circuit 2 from becoming the same potential, and prevents the output level from falling. As a result, noise can be removed from the output waveform and access time can be shortened.

In the above embodiment, by providing the latch circuit 11 in the readout circuit 1, the readout data (output) is
When going from 1'' to rr 1 n and from '0'' to pa 0
Instead of being able to remove the noise that appeared in the output waveform when the read data changes from ``1'' to rr
When changing from Orr or '0'' to "1", it is expected that the fall or rise of the output waveform will be somewhat delayed due to the presence of the latch circuit by the time required to invert it. However, if the latch circuit 11 is inverted The time required to do this can reduce access time delays due to noise in the output waveform to less than half of the time.Accordingly, overall access time can be significantly shortened.

[Effects] A function to latch the read data is added to the readout circuit, which has a transistor that forms a current switch circuit together with the transistor in the flip-flop memory cell. , even if the levels of the higher nodes in the previously selected memory cell and the next selected memory cell simultaneously become lower than the read reference voltage, the previous data is temporarily retained in the read circuit. This prevents current from flowing from the readout circuit toward the pair of common digit lines at the same time when the same binary data is read out in succession, thereby eliminating switching noise from the output waveform and reducing access time. The effect is that the time period is shortened.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the configuration of the latch circuit or the composition ratio of the readout circuit and its peripheral output circuits is not limited to that of the embodiment described above, and various modifications can be considered.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to bipolar static RAM, which is the field of application that formed the background of the invention. static RA
This semiconductor memory device can generally be used in a semiconductor memory device equipped with a readout circuit having a transistor that forms a type of current switch circuit together with other transistors in memory cells.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an example of the configuration of a bipolar static RAM readout circuit, FIG. 2 is a waveform diagram showing changes in each signal in the circuit, and FIG. FIG. 4 is a circuit configuration diagram showing an embodiment of the present invention when applied to a RAM. FIG. 4 is a waveform diagram showing changes in an output signal in the readout circuit. 1...Readout circuit, 2...Output circuit, 3...
・Memory array, 4...X decoder, 5...word line drive circuit, 6...Y decoder, 11...
Latch circuit, 12a, 12b...level shift circuit, MC...memory cell, W...word line, D,
'E...Digital line, CD, CD...Common digit line, Dout...Output terminal. Agent Patent Attorney Akio Takahashi Figure 1 Figure 2

Claims (1)

[Claims] 1. A memory array consisting of flip-flop type memory cells, a readout circuit having a transistor that together with the transistor in this memory cell constitutes a current switch circuit, and a differential output from this readout circuit. and a differential type output circuit for receiving and amplifying the data signal, wherein the reading circuit includes a latch circuit for latching the complementary data signal level read from the memory cell. A semiconductor memory device characterized by: 2. The readout circuit includes two level shifting means,
2. The semiconductor memory device according to claim 1, wherein the level of the output node of the level shift means is latched by a flip-flop type latch circuit. 3. The semiconductor memory according to claim 1 or 2, wherein the differential output of the readout circuit is supplied to the differential output circuit via an emitter follower. Device.