JPS5856876B2 - display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display device in which an image having halftones is displayed on a display device in which a large number of display elements that take two states, on and off, are arranged and used as a display surface.

2. Description of the Related Art Conventionally, display devices in which display elements such as light bulbs and light emitting diodes are arranged in a matrix have been used as large-screen display devices such as scoreboards in stadiums or flat panel display devices.

The method for displaying images with halftones in these display devices is to control the lighting time of each display element during the image display cycle, and turn off all display elements at the same time.As a result, each display However, according to this method, the time Tc available for determining and controlling the on/off of one display element is equal to the image display cycle Tc.
If the number of F1 halftones is y and the number of display elements is In other words, Tc becomes small, making it difficult to increase the number of intermediate gray levels and the number of display elements.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and the amplitude range of the image signal is roughly divided into m levels, and within this level, this level is further divided into n levels, and the overall result is The image signal is represented by two level signals a and b so that the levels are divided into mXn ways.

This second level signal already turns on (lights up) the display element.
By turning off (extinguishing) the display element using the first level signal a, the number of on/off determinations is reduced, thereby making it possible to easily obtain multiple gray levels.

Embodiments of the present invention will be described below with reference to the drawings.

In Figure 1, 1 is a level judgment circuit, 2 is a memory, 3 is an on/off judgment circuit, 4 is a synchronization signal generation circuit, 5 is a memory address designation circuit, 6 is a row selection on/off control circuit, and 7 is a column selection circuit. The on/off control circuit 8 is a display board on which display elements having a memory function are arranged in a matrix.

The image signal is divided into m levels by the level discrimination circuit 1 as shown in FIG. 2, and then divided into n levels within this one level, resulting in a total of mXn levels.

That is, the image signal is represented by two level signals a and b, where the amplitude is V, and the m-divided level signal is a, and the n-divided level signal is b.

These level signals a and b are stored in the memory 2.

The on/off of the display element is controlled based on this stored level signal.
The explanation will be given according to the figures and FIG.

In FIG. 3, the horizontal axis shows time, the vertical axis shows the corresponding level signal, and in FIG. 4, the horizontal axis shows time.

Now, for example, if we are trying to express 16 gray scales with m = 4 and n = 4, as shown in Figure 3, T
At time B3, the addressing circuit 5 reads out the level signal corresponding to the display element of interest and turns it on.
The off determination circuit 3 generates an on signal if b is 3.

If b is other than 3, it remains off.

Similarly, if b is 2 for the read level signal at time TB2, and if b is 1 at time TB1, an on signal is generated.

The row selection circuit 6 column selection circuit 7 receives the address signal from the address designation circuit 5, designates the row and column of the display board 8, and applies the above-mentioned ON signal to the display element corresponding to the intersection to turn on the display element. (turn on.

Since the display element has a memory function, it maintains an on state (light emission) state until the next off signal is applied.

Next, at time ATo, the level signal a is read out by the addressing circuit 5, and if the on/off determination circuit 3 determines that a is O, an off signal is generated.

Similarly, if a is 1 at time TAl and a is 2 at time TA2, an off signal is generated.

Based on the signal from the addressing circuit 5, the row selection circuit 6 and the column selection circuit 7 select the corresponding display element, and apply an off signal to the selected display element to stop light emission.

In this way, by changing the light emitting time width of the display element in 16 ways, 16 gray levels can be obtained.

Note that when focusing on the entire display panel, it is necessary to scan all the display elements while reading out the level signals corresponding to each display element multiple times from TB3 to TA2. This is done, for example, as shown in FIG. T1. T2゜T3. T, , T
This can be realized by configuring the addressing circuit 5 to read out the level signals from the memory and scan the display elements on the display panel in the following order.

As described above, an image signal is expressed by two level signals a and b, and by controlling the lighting time with one level signal and the light-off time with the other level signal, a halftone display with mXn level gradation is achieved. can be realized.

Here, we have described an example of a circuit that stores a level signal in a memory for easy explanation, but the image signal is converted into a binary code, this binary code is stored in a memory, and the upper bits are transferred to the lower bits in the above-mentioned a. The same holds true if the group corresponds to b.

Furthermore, if the column selection circuit is provided with the function of storing on/off signals for one row, control on a row-by-row basis is also possible, and in this way, it becomes easier to distribute on/off signals to the display board. .

According to the present invention, when displaying mXn halftones, only (m+n 2) determinations are required, instead of (mX'n-1) times in the conventional method. ,
When the display period is constant, it is possible to take a long time for each determination, and when the determination time is constant, it is possible to easily obtain multiple gradations, which is a great practical advantage.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram showing an embodiment of the present invention, Figs. 2 to 4 are explanatory diagrams of the operation of the device shown in Fig. 1, Fig. 2 is a graph showing level division, and Fig. 3 is a diagram showing the operation of the device shown in Fig. 1. FIG. 4 is a timing chart showing the relationship between on/off time and on/off, and FIG. 4 is a timing chart showing the relationship between light emitting elements and scanning. In the figure, 1 is a level discrimination circuit, 2 is a memory, 3 is an on/off judgment circuit, 4 is a synchronization signal generation circuit, 5 is a memory address designation circuit, 6 is a row selection on/off control circuit,
7 is a column selection on/off control circuit, and 8 is a display board.

Claims (1)

[Scope of Claims] 1. A display board in which display elements having a memory function are arranged in a matrix, and an amplitude range of m where the amplitude of an image signal is V.
a level determination portion divided into Xn levels and represented by first and second level signals a and b of -a/m+b/m-n; and a memory for storing the first and second level signals. part and
an addressing circuit for selecting a read address of a level signal from the storage section and a display element of the display board; and a first and second level signal read from the storage section at a predetermined time, corresponding to the time. It has a determination circuit that determines whether the corresponding display element is on or off at that time by comparing it with the given level, and each display is determined based on the on/off determination result for the first level signal (or second level signal). A display device characterized in that an image having halftones is displayed by controlling the on time of an element and controlling the off time based on the determination result of another level signal. 2. The memory section stores an image signal or a binary encoded version of the image signal, and the level of the signal read from the memory section is determined to display an image having halftones. A display device according to claim 1.