JPS5855669B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a field effect transistor having a vertical structure.

A typical bipolar type high frequency, high power transistor has a large number of emitters formed in a stripe pattern to achieve high power, but bipolar transistors are prone to thermal runaway and it is difficult to increase the power of the device.

On the other hand, field effect transistors with a vertical structure do not suffer from thermal runaway and are suitable for high-power devices.

Conventional field effect transistors with a vertical structure include a buried gate structure with a cross-sectional structure as shown in Figure 1, or a diffused gate structure with a cross-sectional structure where the gate is deeply diffused and a channel is formed between the gates, as shown in Figure 2. are being manufactured.

In FIG. 1, a gate 1 is manufactured by diffusing impurities into a semiconductor substrate 2 in a mesh shape and then forming a semiconductor layer 3 by epitaxial growth.

If an attempt is made to narrow the gate spacing in order to increase the frequency, the gates will expand due to autodoping and diffusion during epitaxial growth and will no longer form a channel, so the gate spacing cannot be made very narrow.

Further, since the gate resistance is large, this structure is effective as a low frequency high power device, but is not suitable for high frequency applications.

On the other hand, the diffusion gate structure shown in FIG. 2 has a large junction capacitance because the gate 4 is formed by diffusion.

Also, since the distance between the gates is about a few μ, the gate.

It is difficult to take out the source electrodes so that the sources 5 are not short-circuited.

However, since a metal electrode can be placed over the gate, it is more suitable for high-frequency applications than the buried gate method, but since the gate portion occupies most of the area of the device, this structure is still suitable for high-power applications for high-frequency applications. Not suitable for elements.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a vertical field effect transistor using a self-alignment method, which improves the drawbacks of the conventional vertical field effect transistor and enables high frequency and large power.

The method for manufacturing a semiconductor device of the present invention includes the following steps.

forming a first thin layer having a plurality of openings on one principal surface of a semiconductor substrate of a first conductivity type;
forming an oxide film on the surface of each epitaxial layer; removing the first thin layer; using the oxide film on the surface of the epitaxial layer as a mask to form a semiconductor layer; A step of introducing an impurity of a second conductivity type into the substrate surface to form a second conductive shadow region, and performing ion etching on the upper surface of the epitaxial layer and the surface of the second conductive shadow region to form an exposed surface. forming a metal electrode on each exposed surface by vapor deposition; and electrically connecting a common electrode plate to each metal electrode on the upper surface of each epitaxial layer.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for manufacturing a semiconductor device according to the present invention will be explained in detail below with reference to the drawings.

In Figure 3, 11 is As with a specific resistance of 0.005Ω・α
This is a doped 100N type silicon substrate.

Reference numeral 12 denotes an N-type epitaxial layer with a thickness of 6 μm and a resistivity of 10 Ω·min.

This epitaxial layer is made of silicon tetrachloride (SiC4)
l Obtained by hydrogen reduction at 150°C.

Oxide film 13 (S 102 ) is 70OA, then nitride film 1
4 (S' 3N4) at 10OA, and an oxide film of 15
S io 2 was formed sequentially at 600 OA.

The oxide film 13 is formed to remove the nitride film 14 by plasma etching.

Next, as shown in FIG. 4, the oxide film 15, nitride film 14, and oxide film 13 in the portions that will become the source region are etched with NH4F (ammonium fluoride), plasma, edges, and NH4F, respectively, using a well-known photolithography technique. I removed it.

Next, as shown in FIG. 5, selective epitaxial growth was performed using the oxide film 15, nitride film 14, and oxide film 13 as masks to form an epitaxial layer 16 of 1.2 μm with a resistivity of 5 Ω·min.

This removed debris 16 protruded by 0.3 μm onto the oxide film.

Next, phosphorus Pf was diffused into the epitaxial layer 16 to a thickness of 0.3 μm to form N 16'.

Next, the oxide film 15 is removed and the epitaxial layer 16 is
An oxide film 17 was formed by selective oxidation to a thickness of 0OA.

Next, after removing the nitride film 14 with hot phosphoric acid, the oxide film 13 is removed with NH
It was removed at 4F.

Next, using the oxide film 17 as a mask, boron Bf5X1015
A gate region 18 was formed by implanting ions/cd.

At this time, boron is injected only into the lower part of the hole (
Figure 6).

Next, the oxide film 17 is removed and heated to 1000°C as shown in FIG.
The entire surface of the substrate was oxidized to form an oxide film 19 with a thickness of 200 OA.

Next, the oxide film 19 was removed by ion etching using Ar gas in a direction perpendicular to the substrate.

At this time, the oxide film 19' on the side wall portion is not etched (
Figure 8).

Next, as shown in Figure 9, aluminum @ 3000A
A gate electrode 20 and a source electrode 21 were formed by sequential electron beam evaporation of F200 chromium and F500 A copper.

At this time, these electrodes are patterned in self-alignment with the source and gate portions to form an inverted trapezoidal structure.

The copper was deposited to facilitate subsequent plating.

Also, the source islands are separated from each other and need to be connected.

For this reason, gold plating was applied at an applied voltage of 1.2 .

Since the voltage applied to the gate layer is lower than that of the source layer by the junction voltage, plating is applied only to the source electrode.

The thickness of the plating layer 22 is 20μ, and the distance between the sources is 0.
．． Since it is sufficiently large compared to 8μ, the sources are interconnected.

Next, the N+ silicon piece 23 having an area corresponding to the entire source region and the gold layer 22 were bonded together by thermocompression bonding.

The gold layer 22 and silicon piece 23 were effective in lowering the thermal resistance of the device.

Next, a drain electrode was provided on the substrate to form a device.

According to the present invention, since only one mask is required for photoetching, pitch deviations and misalignment occur during mask production.
There are significant advantages in that very dense patterned masks can be used without any considerations and that high frequency, high power devices can be manufactured easily.

[Brief explanation of drawings]

1 and 2 are sectional views of a conventional field effect transistor, and FIGS. 3 to 9 are sectional views showing an embodiment of the manufacturing method of the present invention in the order of steps. Note that the same reference numerals in the drawings indicate the same or corresponding parts, respectively. 11... Semiconductor base (silicon substrate), 12.
...Epitaxial layer, 13.15.19...
- Oxide film) Sin2), 14...Nitride film (S
i3N4), 20...gate electrode, 21...
. . . Source electrode, 23 . . . Silicon piece (common electrode plate).

Claims (1)

[Claims] 1. Forming a first thin layer having a plurality of openings on one principal surface of a semiconductor of a first conductivity type, and using the thin layer as a mask, forming a first
forming an oxide film on the surface of each of the epitaxial layers; removing the first thin layer; and using the oxide film on the surface of the epitaxial layer as a mask, the semiconductor substrate is A step of introducing impurities of a second conductivity type into the surface to form a second conductivity type region, and performing ion etching on the upper surface of the epitaxial layer and the surface of the second conductivity type region to form an exposed surface. forming a metal electrode on each exposed surface by vapor deposition; and electrically connecting a common electrode plate to each metal electrode on the upper surface of each epitaxial layer. Method.