JPS5853867A - Semiconductor light sensitive element - Google Patents

Abstract

PURPOSE:To obtain a light sensitive element having good characeristic by stacking an n type InP, n<-> type InP on the n type InGaAsR or InGaAs of substrate and surrounding the P<+> type light sensitive region in the N<-> type InP with the Be ion-implanted layer. CONSTITUTION:An n and n<-> InP 12, 13 are stacked on an n<+> type InP/InGaAs substrate 11, and a buffer and light absorbing layer are epitaxially formed in succession. A window 14A is opened on an SiO2 14 formed by the sputtering method using a resist mask 14', Be ions are implanted thereto and a p type protection ring 15 is formed. The films 14', 14 are removed and the surface is covered with the PSG 16 and then annealed. the film 16' is removed and the surface is covered with an Si3N4 16 formed by CVD method, a window 16A is opened, Cd is thermally diffused and thereby a p<+> type light sensitive layer 17 is formed. Thereafter, the film 16 is removed and a protection film 18, electodes 19, 20 are provided. According to this structure, the inclined junction can be obtained in the ion implanting direction, drop of breakdown voltage by the lateral step-wise junction can be compensated by the periphery due to formation of the n<-> type InP layer and thereby a light sensitive element having a protection ring with an excellent characteristic can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an InP/In GaAzP light receiving element suitable for communication using light having a wavelength in the 1 μ band.

Generally, in an avalanche photodiode (APD), a reverse bias near the breakdown is applied to the p-n8 junction so that carriers generated by light are avalanche multiplied. InP/I%GaAzP (or I
%GaAz) based API), in order to reduce the leakage current that occurs when a reverse bias is applied to the light-receiving p-n junction, the p-'n junction is placed on the GaAaP (or InGaAz) light absorption layer. Usually, f is formed within the InP window layer grown during the process. That is, while the depletion layer from the p-n junction is sufficiently expanded into the light absorption layer to obtain sensitivity to the required light receiving wavelength, the p-n junction reverse bias characteristic is determined by 1%2 layers.

In this type of APD, a flcpWi impurity diffusion region is usually formed in a sil InP layer on a light absorption layer on an IMF substrate to obtain the p-5la combination. Although it is desirable for breakdown to occur at the center of the p-% junction, it is known that it is more likely to occur at the periphery of the p-n junction due to electric field concentration.

Therefore, a guard ring has been conventionally provided in order to increase the breakdown voltage around the p-junction, and various structures have been proposed. Next, some of them will be illustrated and explained.

In Fig. 1, 1 is a hollow-type I%P wind layer, 2 is a %
The type region 3 is a p medium type region, and regions 2 and 5 are formed by double ion implantation.

In FIG. 2, 4 is an n-type I-wind layer, 5 is an outer-type I%P semiconductor layer, and 6 is a p+-type impurity diffusion region,
After forming a semiconductor layer 5 on a substrate 4, the semiconductor layer 5 is etched into a mesa shape, and then p-type impurities are diffused.

In both of these conventional examples, the central part has a p"-5-s- configuration, which tends to cause avalanche multiplication, and the peripheral part has a p+-" configuration, so it is easy to cause avalanche multiplication.
It is difficult to cause a knockdown.

However, in the conventional example shown in FIG. 1, silicon (Si) ions are usually implanted to form the elongated region 2, but since silicon has a large atomic weight, it is a region of the light receiving section and a region where a high electric field is applied. There is a high possibility that a large amount of injection damage will remain and adversely affect the characteristics. Furthermore, in the conventional example shown in FIG. 2, it is difficult to stabilize the element by passivation.

In addition, as shown in FIG. 3, the I%P wind layer 7 on the substrate side is used as an outer mold, and a "type I%P semiconductor layer 8 is formed on it", contrary to the idea of each of the conventional examples described above. It is also known that a p-type impurity diffusion region 9 is formed in the semiconductor layer 8 so as to be close to or reach the interface with the 1%1 layer 7 on the substrate side.

In this conventional example, region 9 is formed using cadmium (
cd), but in this case, unless the thickness is at least as thick as the 5-type semiconductor layer 8, for example 2 to 5 μm3 or more, the withstand voltage will drop significantly due to the curvature of the junction in the peripheral area. Tonanashi breaks down in the peripheral area.

When forming the structure shown in FIG. 3 in the I%P window layer to form the multiplication region of the InPAliJ elemental compound APD, the thickness of the epitaxially grown I%P semiconductor layer on the quaternary compound semiconductor layer Approximately 4 to 5 [μ expletives] are required. Current LPII (Liq#Litl Phaza
In the Epitgzy) method, 1%
If two layers are grown for more than 3 microns, swift dislocations are likely to occur, so from this point of view there is a limit to increasing the thickness of the epitaxially grown layer. It is difficult to obtain.

The present invention is a light-receiving element in which a guard ring is formed to alleviate electric field concentration that tends to occur in the peripheral part when a p-junction is formed by simple selective diffusion. To make it possible to provide a product with good characteristics without being subject to restrictions on layer thickness. This will be examined in detail below.

FIG. 4 is a sectional view of essential parts of an embodiment of the present invention.

In the figure, 11 is an IcoP/I%GaAaP (or InGa+Az) substrate, which is actually a 5+ type 1nP
n-type 1nGaAzP (or InGmAi
p) This is a light absorption layer grown epitaxially, but it is omitted from the figure because it does not contribute to the guard ring effect that is the object of the present invention. 12 is the outer mold In1 layer;
16 is a type 1nP layer, 15 is a pm guard ring region,
Reference numeral 17 indicates a p-type medium impurity diffusion region (light-receiving region), 18 an insulating film, 19 a p-side electrode, and 20 a %-side electrode.

Guard ring region 15 in this embodiment is formed by ion implantation of beryllium (B-).

Based on the experiments of the present inventor, the fcp-silicon junction formed by ion-implanting beryllium into a round-shaped ImpP is a sloped junction as shown by curves 1B and C in FIG. Become.

In Figure 5, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth from the surface. Annealing temperature = 750 [℃] Annealing time = 20 [minutes] Annealing atmosphere 2N proverb Activation rate: 6O(-) xj: 2.4 (μculm i) B is Dose amount: 5.2 −”:]
Annealing temperature: 700 ['C) xj: 2.2 [ptribute 1] Others: Same as A, Dose amount: 9.6 Xj: 2.1 (μ) and other conditions were obtained under the same conditions as 2A. The curve indicated by LSS represents the impurity distribution calculated by LSS theory.

It is clear from Fig. 5 that when beryllium ions are implanted into n-1% P and annealed, there is a slight shift from the theoretical distribution. The impurity concentration profile when cadmium is thermally diffused is completely different from that of beryllium, and as seen in FIG. 6, it becomes close to a stepped junction.

The data shown in Figure 6 is based on cadmium phosphorus (CtlP).
l) as a diffusion source using the closed tube method to conduct thermal diffusion at 550°C.
It shows the concentration profile of all cadmium when the test was carried out for 5 hours.

In general, there is a difference in breakdown voltage V between a sloped junction and a stepped junction, depending on the difference in the spread of the depletion layer into the p-type region. Therefore, if the guard ring is formed by an inclined joint with a large VII, breakdown of the peripheral portion can be prevented.

By the way, when an impurity region is formed by ion implantation, the lateral junction is not an inclined junction as in the ion implantation direction, but rather is considered to be close to a stepped junction.

Therefore, since the lateral breakdown voltage is small and the effect of the bending of the bond is added, it is difficult to obtain a breakdown voltage difference with the light receiving area. In the present invention, in order to solve this problem, %-fJ
Depending on the provision of the Id' layer 13, a lateral breakdown voltage difference is generated by a difference in impurity concentration.

Next, the case of manufacturing the embodiment shown in FIG. 4 will be explained with reference to FIGS. 7 to 11.

Refer to FIG. 7 (1) %+ type hge Iw&GmAaP (or Inl;aAz) is grown on the substrate 11 by liquid phase epitaxial growth. I! l ISP layer 12, fraud ""WI%P
The layers 16 are grown to a thickness of about 1 μl and 2 μl, respectively. In this case, s=I
s-'), %""=1~5 X 10"[ewr""
1]. It is practical to grow all of these epitaxially grown layers continuously together with the buffer layer and the light absorption layer.

Refer to FIG. 8 (2) A silicon dioxide film 14 is formed to a thickness of, for example, about 5000 mm (:, 2) by sputtering.

(3) The photoresist film 14' has a thickness of, for example, 2 [
μm].

(4) Patterning the photoresist film 14' and the silicon dioxide film 14 to form the guard ring region window 1
4,4 will be provided.

(5) Using the photoresist film 14' as a mask, beryllium ions are implanted to form the p-type guard ring region 1.
form 5. The implantation energy at this time was 150 [Kg
The dose is 1 x 10"(am-").

(6) After removing the photoresist film 14' and the silicon dioxide film 14, a cap layer 16' of phosphosilicate glass is formed by chemical vapor deposition at a temperature of 750 [°C] for 20 minutes. [
Annealing is performed for 1 minute.

See FIG. 10. (7) After removing the phosphosilicate glass cap layer 16', a silicon nitride film 16 is formed by chemical vapor deposition, and after patterning, a window 16A for forming a light receiving area is formed. do.

(8) Thermal diffusion of cadmium and p+ type optical region 1
7 form. The diffusion conditions at this time were 550 [C] and 1 hour.

See FIG. 11 (9) After removing this edge silicon nitride film 16,
Applying conventional techniques, an anti-reflection coating or passivation insulation 18 and electrodes are formed to complete the light-receiving element shown in FIG. 4.

As can be seen from the above description, according to the present invention, when beryllium is ion-implanted into I%P, an inclined junction can be obtained in the implantation direction, and a stepped junction can be obtained in the lateral direction. The breakdown voltage decreases, but this can be done by increasing the breakdown voltage in the peripheral area by providing a depressed-type I%P layer, etc.
It is possible to obtain a semiconductor light-receiving device having a guard ring structure with good characteristics, and since crystal damage caused by ion implantation does not remain in the light-receiving region of the skeleton element, and there is no restriction on the thickness of the crystal layer. It has good characteristics and is easy to design and manufacture.

[Brief explanation of the drawing]

1 to 3 are sectional views of main parts of a conventional example, FIG. 4 is a sectional view of main parts of an embodiment of the present invention, FIGS. 5 and 6 are diagrams showing impurity concentration distribution, and FIG. 7 is a sectional view of main parts of a conventional example. FIGS. 11 to 11 are sectional views of essential parts of the device at key points in the process for explaining the manufacturing of the embodiment shown in FIG. In the figure, 11 is a substrate, 12 is an sW1% P layer, 13 is an n'' type InP layer, 15 is a guard ring region, 17 is a light receiving region, and 18 is an insulating film. Patent applicant Fujitsu Ltd. agent Patent attorney Gobe Tamamushi (3 others) Figure 5 0 0.4 0.8
+, 2 1.6!Depth from 1st surface Cp
m) Figure 6 Depth from 1m plane (ml) Figure 10 Figure 11

Claims (1)

[Claims] n-type 1nGaAaP or InGa formed on the substrate
Az light absorption layer, a %WIf&P semiconductor layer formed thereon, and a 9%-fJI%P semiconductor layer formed thereon, so as to surround the p+ type light region formed on the "type 1nP semiconductor layer". A semiconductor light-receiving device comprising a p-type guard ring region formed by ion-implanting beryllium.