JPS5852833A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS5852833A JPS5852833A JP56150608A JP15060881A JPS5852833A JP S5852833 A JPS5852833 A JP S5852833A JP 56150608 A JP56150608 A JP 56150608A JP 15060881 A JP15060881 A JP 15060881A JP S5852833 A JPS5852833 A JP S5852833A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- semiconductor device
- point glass
- film
- pellet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8389—Bonding techniques using an inorganic non metallic glass type adhesive, e.g. solder glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置およびその製造方法に関し、特に
、半導体素子を、低融点ガラスによってセラミックパッ
ケージの基体に接着した構造および七の製造方法に＠す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a structure in which a semiconductor element is bonded to a base of a ceramic package using low-melting glass, and a method for manufacturing the same.
接着賂ぜるための作東温１′（接着温度）か約５５０℃
以下の低融点ガラスを用いたシリコン半導体素子（ペレ
ット）のパッケージ基体への搭蒙方法は、一般に、セラ
ミック基体とセラミツタキャップとをガラスによって對
着名ゼるガラス封止型のセラミックパッケージ型半導体
装置に使用されている。前記セラミッタパッケージ型中
導体装置を始めとして、一般に低融一点ガラスを用いた
基体への半導体素子の搭載方法では半導体素子を、直接
低融点ガラスによって、接続基体へ接続せしめているか
、半導体素子と、半導体素子か接着もれるべき、低融点
ガラス層を含むベース“アセンブリとの熱膨張係数差か
大きい場合、あるいけ前記熱膨張係数差がかなり小さく
ても半導体素子（ペレット）か大きい場合には、ペレッ
ト付時の接着温度から常温への温度変化、ま友は半導体
装置の完成後の環境温度変化から受ける熱応力か極めて
大きくなるため、ペレットか破壊されることが知られて
いる。Temperature for bonding: 1' (adhesion temperature) or approximately 550℃
The following method of mounting a silicon semiconductor element (pellet) using low melting point glass onto a package substrate is generally a glass-sealed ceramic package type semiconductor in which a ceramic substrate and a ceramic vine cap are combined with glass. used in equipment. Generally, in the method of mounting a semiconductor element on a substrate using low melting point glass, including the above-mentioned ceramitter package type medium conductor device, the semiconductor element is directly connected to the connection substrate by low melting point glass, or the semiconductor element and If the difference in coefficient of thermal expansion between the semiconductor element and the base assembly containing the low-melting glass layer is large enough to cause adhesive leakage, or even if the difference in coefficient of thermal expansion is quite small, if the semiconductor element (pellet) is large. It is known that the pellets can be destroyed due to extremely large thermal stress caused by the temperature change from the bonding temperature at the time of attaching the pellet to room temperature, or by the environmental temperature change after the semiconductor device is completed.
ところか、従来は、ペレットがどのようなメカニズムに
より破壊に至るかとｂうＣとか判明していなかった。そ
のため、従来は、低融点ガラスを用いた半導体素子の搭
載技術は製造原価を低減できる一大長所が一般に認めら
れながら、半導体素子の大１１モ、るるいはベースアセ
ンブリの材ｌｐ＃か限定逼れた範囲内でしか使用嘔れて
いなかった。However, until now, it was not clear what mechanism led to the destruction of pellets. Therefore, conventionally, although it is generally recognized that mounting technology for semiconductor elements using low-melting glass has the great advantage of reducing manufacturing costs, it has been limited to the size of the semiconductor element, the base assembly material LP#, etc. It was only used within the specified range.
例えば、従来のセラミックパッケージ型半導体装置にお
いて、セラミック基体に１低ｗｌｊ点ガラスによって、
シリコンベレット管接着する場合、約３．０−角取上の
サイズｔもつシリコンベレットの接着は、接着時にその
シリコンペレット内にクラックか生じ、結果的に低融点
ガラスの接着法の採折
用は不偉能でめった。For example, in a conventional ceramic packaged semiconductor device, a low wlj point glass is used on a ceramic substrate.
When gluing silicone pellet tubes, cracks occur in the silicone pellets when gluing silicone pellets with a size t above 3.0-square cut, and as a result, it is difficult to adopt a gluing method for low-melting glass. I was very incompetent.
本発明はこのような従来技術の欠点を解消するためにな
嘔れたもので、前述の如く、半導体素子とベースアセン
ブリとの熱膨張係数差か大きい場合でも、サイズの大き
い半導体素子を破壊せずに接続帯Ｈぜしむろ低融点ガラ
スによる接着方法を提供すること【目的とするものであ
る。The present invention has been developed to overcome the drawbacks of the prior art, and as described above, even if the difference in thermal expansion coefficient between the semiconductor element and the base assembly is large, it is possible to destroy a large semiconductor element. It is an object of the present invention to provide a method of bonding a connecting zone H using low melting point glass.
本発明は、従来の低融点ガラスの接着方法によ４シリコ
ンペレツトのクラックの発生又は破壊ノ現象のメカニズ
ムについて、本発明者等が実験、研究によって解析した
結果なされｔものである。The present invention was made as a result of experiments and research conducted by the present inventors to analyze the mechanism of cracking or destruction of silicon pellets by the conventional bonding method of low melting point glass.
本発明者等が鋭意研究を重ねた結果、前記し友半導体素
子すなわちペレットが破壊する現象は、半導体素子の構
成材料であるシリコン（Ｂ１）かベース７センブリの一
部として予めセラミック基体の表面に被着逼れた低融点
ガラス膜との接着強度が弱りため熱応力か加えられると
容易に低融点ガラスとの間で接合部の剥離か生じ、これ
によって上記剥離部の境界部にシリコンペレットを破壊
ゼしめるような応力の集中が生ずるために起きるもので
あることが判明した。この現象を第１図全参照にして説
明する。第１！＆！Ｊ［おいて、低融点ガラス膜２を予
め形成しておい友セラミック基体１に、既にその表面に
回路素子か形成逼れたシリコンペレット４を約４００℃
〜４５０℃の周囲温度のもとで、ガラス膜２ｔ−溶融せ
しめることによって、接着名ゼる場合、ガラス１Ｉ４２
の冷却時において、ガラス膜２とシリコンペレット４と
の熱膨張係数のＭＶｃより、圧縮力Ｐか、シリコンペレ
ット４を曲げるように作用する。この時、シリコンのｊ
１膨張係数は約３．５ Ｘ １０−”／’Ｃで、世融点
ガラスの熱膨張係数は約５８１０−＠〜６×１０−’／
Ｃであることか注目される。これによってガラス膜とシ
リコンペレットとの間の接着強度が弱いために、領域ム
に剥離會生じる。領域ムにおいて、シリコンペレット番
とガラス！ｓ２との間に剥離か生じた場合け、剥離部の
境界部ＭＫシ込て、シリコンベレット４の内部に応力が
集中し、これによってシリコンベレットにクラック０が
生じることか判明した。As a result of extensive research by the present inventors, we have found that the above-mentioned phenomenon in which the semiconductor element, that is, the pellet breaks down, is caused by the fact that silicon (B1), which is the constituent material of the semiconductor element, is pre-coated on the surface of the ceramic substrate as part of the base 7 assembly. The adhesive strength with the tightly adhered low-melting glass film weakens, and when thermal stress is applied, the joint between the low-melting glass and the low-melting glass film easily peels off. It was found that this was caused by the concentration of stress that led to the collapse. This phenomenon will be explained with full reference to FIG. 1st! &! A silicon pellet 4 with circuit elements already formed on its surface is heated to about 400°C on a ceramic substrate 1 on which a low melting point glass film 2 has been previously formed.
By melting the glass film 2t under an ambient temperature of ~450°C, the adhesive properties of the glass 1I42 are reduced.
During cooling, the compressive force P acts to bend the silicon pellet 4 due to the thermal expansion coefficient MVc of the glass film 2 and the silicon pellet 4. At this time, silicon j
1 expansion coefficient is about 3.5 x 10-''/'C, and the thermal expansion coefficient of melting point glass is about 5810-@~6 x 10-'/'
The fact that it is C is attracting attention. As a result, the adhesive strength between the glass film and the silicon pellets is weak, resulting in peeling in some areas. In the area, silicon pellet number and glass! It has been found that when peeling occurs between the silicon pellets 4 and s2, stress is concentrated inside the silicon pellet 4 at the boundary MK of the peeled portion, and this causes cracks to occur in the silicon pellet.
この解析結果は、本発明に従う解決原理を示唆せしめた
。すなわち、接着用低融点ガラス１１１ｉＫシリコンペ
レツトか剥離することなく強固に接着逼れれば、局部的
な剥離にもとづく、シリコンベレットへの応力の集中は
防止され、これによって、シリコンベレットの破壊を防
止することかできるという技術思想か与えられた。This analysis result suggested the solution principle according to the present invention. In other words, if the low melting point glass 111iK silicon pellet for adhesion is firmly adhered without peeling, stress concentration on the silicon pellet due to local peeling is prevented, thereby preventing the silicon pellet from breaking. We were given a technical idea of what we could do.
本発明はこの技術思ＲＫ基づいてな嘔れたもので、低融
点ガラス膜によって接着されるシリコンベレットの裏面
に、低融点ガラスとの濡れ性かよく、かつ接着強度がシ
リコンのそれよりも大きい接着補強膜を予め形成ゼしめ
ることｔ％黴とするつ以下、本発明の実施例について図
ｒＭを参照して鋺明する。The present invention was developed based on this technical consideration, and the back side of the silicone pellet is bonded with a low-melting point glass film, which has good wettability with the low-melting point glass and has a bonding strength greater than that of silicone. Embodiments of the present invention will be described below with reference to Figure RM.
第２図シよび第３図は本発明の実施例を蜆明するための
図面で、第２図は本発明によシ牛導体素子をパンケージ
のベレット取付面に＠−載する前の状ｌＩ！を示す枦略
断面図、第３図は搭載後の状ｓｒ示す積略断面図である
。図示した実施例において、ｌｔセラミックパッケージ
の一部であるセラミック基体。２ｔｊセラミック基体１
のキャビティ部（ペレット取付１ｌｌ）に形成された半
導体素子接続用の低融点ガラス膜。この低融点ガラス膜
として、接着温度か５５０℃以下（軟化点か約５００℃
以下）のものか選択される。この種のガラス膜のガラス
成分の一例は次の組成をもつ。Figures 2 and 3 are drawings for explaining the embodiment of the present invention, and Figure 2 shows the state of the conductor element according to the present invention before it is mounted on the bellet mounting surface of the pan cage. ! FIG. 3 is a schematic cross-sectional view showing the state after mounting. In the illustrated embodiment, the ceramic substrate is part of an lt ceramic package. 2tj ceramic base 1
A low melting point glass film for connecting semiconductor elements formed in the cavity part (pellet mounting 1ll). This low melting point glass film has a bonding temperature of 550°C or less (a softening point of approximately 500°C).
(below) is selected. An example of the glass component of this type of glass film has the following composition.
ＰｂＯ−７０重量％
Ｂ雪０ｓＩＯ重量％
Ｔｉｌｌ
ｓｔｏｗ ２０重量％
ＺｒＯ■
嘔らに１このガラス膜の中に熱！＃張係数ｔＸ整するた
めのフィラーとしてＰＩ）Ｔｉｌｌか含まれる。PbO - 70% by weight B snow 0sIO weight% Till stow 20% by weight ZrO ■ There's heat inside this glass membrane! #PI)Till is included as a filler to adjust the tension coefficient tX.
この低融点ガラスの熱膨張係数は、例えば５ｘ１０−＠
〜６Ｘ１０”−’／’Ｃで、接着温度か４００〜４５０
℃である。The thermal expansion coefficient of this low melting point glass is, for example, 5x10-@
~6X10"-'/'C, bonding temperature 400-450
It is ℃.
低４１点ガラスｓ２は、印刷技術によってキャビティｍ
Ｋ＠布することかてきる。Low 41 point glass s2 has cavity m by printing technology
K＠It comes to cloth.
３Ｆｉ封止用低融点ガラス展である。後者の低融点ガラ
ス膜３Ｆｉ上記キヤビテイ部の半導体素子接続用の低融
点ガラス膜２と同一材質でもよく、また異なる材質のも
のを用いてもよい。前記セラミック基体１、抵融点ガラ
ス２と３ｔｆ総称的にペースアセンブリと呼ぶことかで
きる。This is an exhibition of low melting point glass for 3Fi sealing. The latter low melting point glass film 3Fi may be made of the same material as the low melting point glass film 2 for connecting semiconductor elements in the cavity portion, or may be made of a different material. The ceramic substrate 1, the low melting point glass 2 and 3TF can be collectively referred to as a pace assembly.
ま九、符号４ｔｊキャビティ部の低融点ガラス膜２に接
続搭載されろべきシリコン半導体素子丁な？） チＶ
’） ＝ｙ ｙ ベレット。このシリコンペレッ）［は
、牛導体集槓回路技＃ＩＫよって複数の回路素子、例え
ばＭＯ８１１１？Ｑか形成賂れている。このシリコンベ
レットは、例えば、５■角の太き名をもつ。このシリコ
ンベレットのシリコン材料自体の慶膨張係数は約３．５
Ｘ１０−＠／Ｃである。Ninth, is there a silicon semiconductor element that should be connected and mounted on the low melting point glass film 2 in the cavity section? ) ChiV
') =y y Beret. This silicon pellet) [is a cow conductor integrated circuit technology #IK with multiple circuit elements, for example MO8111? Q or forming a bribe. This silicone pellet has, for example, a thick name of 5 squares. The coefficient of thermal expansion of the silicon material itself of this silicon pellet is approximately 3.5.
It is X10-@/C.
５ｒｊ牛導体素子４の裏面に設けられた接着補強膜で、
半導体装置の製造プロセスで配線としてよく使用もれる
アルｊニウム（ムｔ）属を使用することかできる０幽示
した例は、約１μ淋の厚″６ｔ−もつムを蒸着膜でるる
。なお、このムを蒸着膜５のムＬＩ／ｉ蒸着のみによら
ず、スパッター岬他の方法で形成されて屯よい。With the adhesive reinforcement film provided on the back side of the 5rj cow conductor element 4,
An example of the use of aluminum, which is often used as wiring in the manufacturing process of semiconductor devices, is a vapor-deposited film with a thickness of approximately 1 μm and a thickness of 6T. However, this layer of the vapor deposited film 5 may be formed not only by LI/i vapor deposition but also by other methods such as sputtering.
接着補強膜５としてムを蒸着膜管使用する一つの有利な
点は、上記したように、配線プロセスなどで使用される
ムｔの蒸着装置を兼用できることにある。このムｔＨの
中には、数重童％のシリコン（Ｓｌ）か原人もれても曳
い。接着補強膜５としては、酸化アルミニウムムＡｓｈ
ｓ ｋ使用することもできる。しかしながら、この接着
補強ａＳ＃ｉ、大きなウェーハから、スクライビング’
Ｍｔ＊によって小さなペレットに分離もれる以前に、ウ
ェーハ全体に形成されるものであるから、ペレットへの
分離後に、個々のペレットの電気的特性を検査する際、
ペレットｓ面は、検査時の一電極として働くよう、導電
性であることか望ましい。この点において、ムｔｅａｓ
展の使用よシムを膜の使用の方か有利である。One advantage of using a vapor deposition film tube for the adhesive reinforcing film 5 is that, as described above, it can also be used as a vapor deposition apparatus for the vapor deposition device used in wiring processes and the like. In this MutH, even if some silicon (Sl) or a hominid is leaked, it will be drawn. The adhesive reinforcing film 5 is made of aluminum oxide Ash.
s k can also be used. However, with this adhesive reinforcement aS#i, scribing'
Since it is formed on the entire wafer before it is separated into small pellets by Mt*, when inspecting the electrical characteristics of individual pellets after separation into pellets,
It is desirable that the S-plane of the pellet be electrically conductive so as to serve as one electrode during inspection. In this respect, Muteas
The use of shims is more advantageous than the use of membranes.
接着補強膜５として、ムｔＷＳ以外に、低融点ガラス膜
と接着強度の大きい金属の膜としてクロム（Ｏｒ）、チ
タｙ（Ｔｌ）およびｆｌ１４ｃ口ｕ）ｋｌ史用すること
かできる。これらの金属膜の使用も、ペレットの裏面の
電極として作用させることができるから、ペレット検査
時に有利となる。金属膜の使用のうち、特にアルＳニウ
ム膜の使用け、加工性、接着性および製造コストの京か
ら有利である。As the adhesion reinforcing film 5, in addition to MutWS, chromium (Or), titanium (Tl), and fl14c-kl can be used as metal films having high adhesion strength to a low-melting glass film. The use of these metal films is also advantageous when inspecting pellets since they can act as electrodes on the back surface of the pellet. Among the metal films, the use of an aluminum S film is particularly advantageous because of its workability, adhesion, and manufacturing cost.
第２因において図示されていないけれども、ペースアセ
ンブル６は、パッケージとしての外部引出しリードを持
って−ろ。ｔ７ｊ、ベースアセンブリ６［Ｆｉ、セラミ
ックのキャップ（□示されていない）か低融点ガラス膜
３によって接着され、これによって半導体素子番は封止
嘔れる。Although not shown in the second factor, the pace assembly 6 has an external lead as a package. t7j, the base assembly 6 [Fi is adhered by a ceramic cap (not shown) or a low melting point glass film 3, thereby sealing the semiconductor element number.
次に、本発明の方法により半導体素子ｔパッケージにＳ
値する手順について説明する。Next, by the method of the present invention, S
Describe the steps worth taking.
まず、セラミック基体１、低融点ガラス膜２と３からな
るペースアセンブリｔ％ ４００℃〜４５０Ｃの低融
点ガラスの作業温−（接着温度）にまで加熱して低融点
ガラスｊ［２を軟化ゼしめ几状謬で、裏面にムを蒸着ｊ
Ｉ１６會設けた半導体素子４ｔその中央部のペレット取
付面上に真空吸着書構をもつコレット（図示されていな
い）によって位置さぞ、コレットｔ−Ｏしてペレットに
対し４ｇ／ｃｄ！度の加重音訓える。この状捗で低融点
ガラス２とＡＡ蒸着膜５とか互いに濡れ合って接着ちれ
、互いに強固に接合ちれるように、所定の時間、例えば
１秒間加熱した後、冷却を行うことにより、半導体素子
４のペレット取付面への搭１１１！接′Ｎ１か完了する
。First, the pace assembly consisting of the ceramic substrate 1 and the low melting point glass films 2 and 3 is heated to the working temperature of the low melting point glass of 400°C to 450°C (adhesion temperature) to soften and zeify the low melting point glass J [2]. Mu is vapor-deposited on the back side with a precise pattern.
The semiconductor element 4t provided in the I16 assembly is positioned by a collet (not shown) having a vacuum suction structure on the pellet mounting surface in the center, and the collet t-O is 4 g/cd against the pellet! You can learn the weighted sound of degree. In this situation, the semiconductor element is heated for a predetermined period of time, for example, 1 second, and then cooled so that the low melting point glass 2 and the AA vapor deposited film 5 get wet and adhere to each other and are firmly bonded to each other. Tower 111 on the pellet mounting surface of 4! Connection 'N1 is completed.
ペレット４の１１面へアルミニウム膜ｓｔｓ用すること
によって、ガラス膜のアルＳニウム膜への濡れ性および
接着性が改善ちれるので、加熱、接着時にシいそ、ペレ
ット４に対する過度な加電は不要となる。本発明によれ
ば、第４図に示すように、シリコンペレット番の取付Ｗ
６會接看用ガラス＠２の中に埋込むような大きな加圧Ｇ
ｔ−必要としないので、コレット７の加圧Ｇによるペレ
ット４のエツジｓ８の割れｔ防止丁番ことかできる。こ
れに対し、従来の方法によれば、シリコンペレットは、
ガラス膜とシリコンペレットとの間の接着強度か弱かっ
たために、シリコンベレツｉｔガラス展の中に埋込むよ
うに、接着時に、コレットによって本発明の５倍以上の
加圧をベレン）Ｋ加える必要かあった。これは、ペレッ
トに割れを生じ毛ゼ友。本発明によれば、このような作
業上の不良の発生を減少名ゼることができる。By applying the aluminum film sts to the 11th side of the pellet 4, the wettability and adhesion of the glass film to the aluminum film are improved, so there is no need to apply excessive electricity to the pellet 4 during heating and bonding. becomes. According to the present invention, as shown in FIG.
6 Large pressurized G that can be embedded in the viewing glass @2
Since t is not required, the hinge can be used to prevent the edge s8 of the pellet 4 from cracking due to the pressure G of the collet 7. On the other hand, according to the conventional method, silicon pellets are
Because the adhesive strength between the glass film and the silicon pellet was weak, it was necessary to apply more than 5 times the pressure of the present invention using a collet during adhesion to embed it in the silicon pellet. Ta. This causes cracks in the pellet and causes hair loss. According to the present invention, the occurrence of such operational defects can be reduced.
本実施例においては、ムＬ蒸着膜５かペレット取付部の
低融点ガラス膜２と強固に、しかもムを膜の全面におい
て接合されるので、半導体素子４か破ｌ１１１れてしま
うような熱応力は半導体装置か使用ちれるべき如何なる
環境条件下に於ても生ずることはなく良好な半導体素子
４の搭載が完成される。In this embodiment, since the mulch vapor-deposited film 5 is firmly bonded to the low melting point glass film 2 of the pellet attachment part, and the laminate is bonded over the entire surface of the film, thermal stress that could cause the semiconductor element 4 to break is avoided. This does not occur under any environmental conditions under which the semiconductor device is used, and the mounting of the semiconductor element 4 is completed in good condition.
本発明に従えば、シリコンペレットのサイズか約３１角
以上のものでも、り２ツク又は破壊なしに１ガラス臘に
よる七う２ツク基体への取付けが回部となった。上述の
実施例では５１角のシリコンペレットの取付けｔ示しｔ
が、５■角以上の取付けも可能である。According to the present invention, even silicon pellets larger than about 31 squares in size can be attached to a seven to two base substrate using one glass frame without peeling or destruction. In the above example, the attachment of a 51 square silicon pellet is shown as t.
However, it is also possible to install more than 5 squares.
な訃、上述の実施例では、シリコンペレットを取付ける
基体の材料としてセラミックの鳩舎について毅明したか
、セラミックの変υに、ベリリア音便用することもでき
る。However, in the above-mentioned embodiments, ceramic pigeonholes are used as the material for the substrate on which the silicon pellets are attached, but beryllia can also be used in ceramic variants.
以上説明したように、本発明によれば、半導体素子を破
壊する仁となく、確実かつ強固に搭載することができ、
またペレット付けのために高価な金等の貴金属を用いる
必要がないので、半導体装置の；ストを着しく低減でき
る。As explained above, according to the present invention, it is possible to mount a semiconductor element reliably and firmly without damaging the semiconductor element.
Furthermore, since there is no need to use expensive precious metals such as gold for attaching pellets, the cost of the semiconductor device can be significantly reduced.
第１図は、従来技術に従う半導体装置の構造を示す断面
図；
第２図は、本発明に従う半導体装置における半導体素子
ｔペースアセンブリに取付けする前の半導体素子訃よび
ベースアセンブリの断面図；第３図は、本発明に従う半
導体装置における、半導体素子をベースアセンブリに取
付けした後の状ｌ１ｔ−示す断面図；および
第４図は、本発明に従う他の半導体装置の断面図である
。
１・・・セラミック基体、２・・・低融点ガラス躾、３
・・・封止用低融点ガラス族、４・・・シリコン牛導体
ベレット、５・・・接着補５！１換、６・・・ベースア
センブリご７・・・コレット。
代理人 弁理士 薄 １）利 幸
第 １ 図
第 ２ 図
第 ３ １１
第 ４ 図
゛ＣFIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to the prior art; FIG. 2 is a cross-sectional view of a semiconductor device and base assembly before being attached to a semiconductor device T-pace assembly in a semiconductor device according to the present invention; The figure is a cross-sectional view showing a semiconductor device according to the present invention in a state after a semiconductor element is attached to a base assembly; and FIG. 4 is a cross-sectional view of another semiconductor device according to the present invention. 1...Ceramic base, 2...Low melting point glass base, 3
...Low melting point glass group for sealing, 4.Silicone conductor pellet, 5.Adhesion supplement 5!1 replacement, 6.Base assembly 7.Collet. Agent Patent Attorney Susuki 1) Toshiyuki 1 Figure 2 Figure 3 11 Figure 4 ゛C
Claims (1)
ットを接着するための半導体装置の製造方法において、
前記低融点ガラスか接着逼れるべき前記シリコンペレッ
トの裏面に、前記低融点ガラスと濡れ性がよく、かつ前
記低融点ガラスとの接層強健が、前記シリコンペレット
のそれよシ大きい接着補強膜を予め形成丁ゐことを特徴
とする半導体装置の製造方法。 ２、前記接着補強膜は金ｗ４換でめることｔ特徴とする
特許請求の範囲第１項記載の半導体装置の製造方法。 ３、 ＠配金属躾は、アルミニウム展でめることｔ特
徴とする特許請求の範８ＪＩ２項配電の半導体装置の製
造方法。 ４、前記金１Ｉ４１１４は、クロム、チタン訃よび銅か
ら遍ＩＲされた一つの金属の膜でるることｔ脣値とする
％許−求の範囲第２項記載の半導体装置の製造方法。 ＆ 前記接着補強膜は、酸化アルミニウムの膜であるこ
とｔ特徴とする特許請求の範囲第１項記載の半導体装置
の製造方法。 ６、前記絶縁基体は、セラミック基体で、前記舒融点ガ
ラスは５００℃以下の軟化点ｔもつことｔ％値とする特
許請求の範囲第１項乃至＠５項記載の半導体装置の製造
方法。 ７、平らな一面を持つセラミック基体と、前記セラミッ
ク基体の前記平らな表面に接着された低融点ガラス膜と
、シリコンペレットと、前記シリコンペレットの裏面に
儂着もれ、かつ、前記低融点ガラス膜に接着された、前
記低融点ガラス族との接着強度か、前記シリコンペレッ
トの場合よりも大きい接着補強膜とから成ることｔ特徴
とする半導体装置。 ８、前記接ｍ″ｆ＃Ａ強換は、アルミニウム農でめるこ
とｔ−特徴とする籍許時求の範囲第７項記載の半導体装
置。 ９、前記接着補強膜は、クロム、チタンおよび銅から選
択された一つの金属の膜であることを特徴とする特許請
求の範囲第７項記載の半導体装置。 １０、前記接着補強膜は、酸化アルミニウム膜であるこ
とｔ特徴とする特許請求の範囲第７項記載の半導体装置
。 １１、 前記低融点ガラス膜の軟化点け５００℃以下
であること資特徴とする特許請求の範囲第７項乃至第１
０項記載の半導体装置。[Claims] 1. A method for manufacturing a semiconductor device for bonding silicon pellets to an insulating substrate using low-melting glass,
On the back side of the silicone pellet to which the low-melting point glass is to be bonded, an adhesion reinforcing film is provided which has good wettability with the low-melting point glass and has a stronger contact layer with the low-melting point glass than that of the silicone pellet. A method for manufacturing a semiconductor device, characterized in that it is formed in advance. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the adhesive reinforcing film is plated with gold (W4). 3. A method for manufacturing a semiconductor device with power distribution as claimed in Claim 8JI(2), characterized in that the metal distribution is made of aluminum. 4. The method for manufacturing a semiconductor device according to item 2, wherein the gold 1I4114 is a single metal film which is uniformly IR-treated from chromium, titanium, and copper. & The method of manufacturing a semiconductor device according to claim 1, wherein the adhesion reinforcing film is an aluminum oxide film. 6. The method of manufacturing a semiconductor device according to claims 1 to 5, wherein the insulating substrate is a ceramic substrate, and the melting point glass has a softening point t of 500° C. or less. 7. A ceramic substrate having one flat surface, a low melting point glass film bonded to the flat surface of the ceramic substrate, a silicon pellet, and the low melting point glass film adhering to the back surface of the silicon pellet; 2. A semiconductor device characterized in that the semiconductor device comprises an adhesion reinforcing film bonded to the film and having an adhesive strength greater than that of the silicon pellet. 8. The semiconductor device according to item 7, wherein the contact m″f#A reinforcement is made of aluminum. 9. The adhesive reinforcing film is made of chromium, titanium, and copper. 10. The semiconductor device according to claim 7, characterized in that the adhesive reinforcing film is an aluminum oxide film. The semiconductor device according to claim 7. 11. Claims 7 to 1, characterized in that the softening point of the low melting point glass film is 500° C. or lower.
The semiconductor device according to item 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56150608A JPS5852833A (en) | 1981-09-25 | 1981-09-25 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56150608A JPS5852833A (en) | 1981-09-25 | 1981-09-25 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5852833A true JPS5852833A (en) | 1983-03-29 |
Family
ID=15500597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56150608A Pending JPS5852833A (en) | 1981-09-25 | 1981-09-25 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5852833A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4871405A (en) * | 1988-03-30 | 1989-10-03 | Director General, Agency Of Industrial Science And Technology | Method of bonding a semiconductor to a package with a low and high viscosity bonding agent |
| US4897704A (en) * | 1983-01-10 | 1990-01-30 | Mitsubishi Denki Kabushiki Kaisha | Lateral bipolar transistor with polycrystalline lead regions |
-
1981
- 1981-09-25 JP JP56150608A patent/JPS5852833A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4897704A (en) * | 1983-01-10 | 1990-01-30 | Mitsubishi Denki Kabushiki Kaisha | Lateral bipolar transistor with polycrystalline lead regions |
| US4871405A (en) * | 1988-03-30 | 1989-10-03 | Director General, Agency Of Industrial Science And Technology | Method of bonding a semiconductor to a package with a low and high viscosity bonding agent |
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