JPS5852761A - Program check system - Google Patents

Program check system

Info

Publication number
JPS5852761A
JPS5852761A JP56151674A JP15167481A JPS5852761A JP S5852761 A JPS5852761 A JP S5852761A JP 56151674 A JP56151674 A JP 56151674A JP 15167481 A JP15167481 A JP 15167481A JP S5852761 A JPS5852761 A JP S5852761A
Authority
JP
Japan
Prior art keywords
program
instruction
display
execution
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56151674A
Other languages
Japanese (ja)
Inventor
Kazusuke Koba
木場 一輔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Facom Corp
Original Assignee
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Facom Corp filed Critical Fuji Facom Corp
Priority to JP56151674A priority Critical patent/JPS5852761A/en
Publication of JPS5852761A publication Critical patent/JPS5852761A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To check a program easily by displaying data on the execution of every instruction of the program to be checked on a display part every time one instruction of the program is executed. CONSTITUTION:A counter 3 is driven and step-advanced by the start instruction ST of a tracer T, generating an interruption instruction B. Once this interruption instruction B is received by an interruption acceptance part 4, a control part 5 reads an execution instruction S1 out of the starting address A1 of a program P to be checked by a next instruction of the tracer T, and then executes the instruction. The control part 5 saves data of registers R0 and R, and a stack pointer SP in a memory 6. Then, a display control part 7 is actuated by a control signal E to display data D in the memory 6 on a display part 8. When the displayed data has no error, a keyboard 9 is operated to generate a start signal F by the display control part 7, thereby displaying the execution state and results of a program to be checked on the display part 8.

Description

【発明の詳細な説明】 本発明はプログラムの実行状態を調べて検査するプログ
ツム検査方式に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program inspection method for examining and inspecting the execution state of a program.

アセンブラ言語で組まれたプログラムを検査する一方法
に、テストプログラム()レーザ)を用いる方法がある
。これは予め被試プログラムの主要箇所(ステップ)に
ブレークポイントを設け、これに5VC(スーパーバイ
ザ呼出し)命令を設定しておく、そして、との被試プー
ダラムを実行せしめたとき、主要ステップの命令を実行
する毎に、その実行状態を出力せしめて、これをチェッ
クする方式である。このような従来方式は、主要箇所間
でプログラムの暴走(プログラム建スによるループ状態
)等を生じた場合に原因を把握できない欠点を有する。
One method for testing programs written in assembler language is to use a test program (laser). This is done by setting breakpoints in advance at the main points (steps) of the test program, setting 5VC (supervisor call) commands therein, and when executing the test poodaram, the commands of the main steps are executed. This method outputs the execution status each time it is executed and checks it. Such conventional methods have the disadvantage that when a program runaway (loop state due to program construction) occurs between major locations, the cause cannot be ascertained.

本発明は上記の欠点を解決するために表されたもので、
プログラムの検査を容易とするプログラム検査方式の提
供を目的とする。
The present invention is presented to solve the above-mentioned drawbacks,
The purpose is to provide a program inspection method that facilitates program inspection.

本発明は、処理装置と、メそすと1表示部とで構成され
、被検査プログラムを前記処理装置で実行させることに
よシ、誤りを検査するプログラム検査方式において、前
記被検査プログラムの1命令を実行する毎に歩進するカ
ウンタと、該カウンタが歩進される度びに前記処理装置
の制御プログラムに対し割込み命令を発する手段とを備
え、該割込み命令を受付けた前記処理装置が前記被検査
プログツムの1命令を実行したのち、該実行結果及び実
行状態のデータを前記メモリに格納し、該格納されたデ
ータを前記表示メモリに格納して表示せしめることKよ
シ検査することを特徴とするプ田グ2ム検査方式である
The present invention provides a program inspection method that includes a processing device, a display section, and a display section, and checks for errors by executing the program to be inspected by the processing device. A counter that increments each time an instruction is executed, and means that issues an interrupt instruction to the control program of the processing device each time the counter is incremented, the processing device receiving the interrupt instruction After executing one instruction of the inspection program, the execution result and execution state data are stored in the memory, and the stored data is stored in the display memory and displayed. This is a programmable inspection method.

以下、方発明を図面によって説明する。図面は本発明の
一実施例を説明するブ四ツク図であシ、1.6はメモリ
、2は固定領域、3はカウンタ、4は割込受付部、5は
制御部、フは表示制御部、8は表示部、9はキーボード
、人、1人、、Anはアドレス、Bは割込命令、Cはコ
ンディV1ンコード、Dはデータ、Eは制御信号、FF
i起動信号、ICはアドレスカウンタ、LP8Wはロー
ドB8W命令、Pは被検査プログツム、R,Roはレジ
スタ、8はスティタス情報s 81  + s、  I
 anは実行命令、8Fはスタックポインタ、8Tは起
動命令、Tはトレ←す(検査プログラム)である。
The invention will be explained below with reference to the drawings. The drawing is a block diagram for explaining an embodiment of the present invention, in which 1.6 is a memory, 2 is a fixed area, 3 is a counter, 4 is an interrupt reception section, 5 is a control section, and F is a display control section. section, 8 is the display section, 9 is the keyboard, 1 person, An is the address, B is the interrupt command, C is the control V1 code, D is the data, E is the control signal, FF
i start signal, IC is address counter, LP8W is load B8W instruction, P is program to be tested, R, Ro are registers, 8 is status information s81 + s, I
An is an execution instruction, 8F is a stack pointer, 8T is a startup instruction, and T is a trace (inspection program).

図面におけるメモリ1の固定領域2には、被検査プログ
ツムPの先頭アドレスAIが格納されており、1命令が
実行される毎に更新(人、→人冨→・・・人n)される
ものとする。またカウンタ3が歩進する毎に割込命令B
が発せられる。図面において、まずトレーサTの起動命
令8Tによシカウンタ3が起動されて歩進し、割込命令
Bが発せられゐ。この割込命令Bを割込受付部4が受付
けると、制御部5は、トレーサTの次の命令(LP8W
)によシ被検査プpグラムPの先頭アドレスA1の実行
命令S1を取出し、これを実行せしめる。次に制御部5
は、レジスタR0(スティタス情報S。
In the fixed area 2 of the memory 1 in the drawing, the start address AI of the program P to be tested is stored, and is updated (person, → person tom → . . . person n) every time one instruction is executed. shall be. Also, every time counter 3 increments, interrupt command B
is emitted. In the drawing, first, the counter 3 is activated and incremented by the activation command 8T of the tracer T, and an interrupt command B is issued. When the interrupt reception unit 4 receives this interrupt command B, the control unit 5 receives the next command (LP8W
) extracts the execution instruction S1 at the start address A1 of the p-gram P to be inspected and executes it. Next, the control section 5
is register R0 (status information S.

コンディジ■ンコードC,アドレスカウン)IC)、レ
ジスタ8(実行結果など)及びスタックポインタSPの
データをメモリ6に8AVBせしめる。然るのち制御信
号Eにより表示制御部7が起動され、メモリ6内のデー
タDが表示部8に表示される。検査者はこの表示された
データを調べることによシ誤シの発見に努める。異常が
ない場合には、キーボード9を操作すれば1表示制御部
7から起動信号yが発せられAc、このため再びトレー
サTが作動し、カウンタ3が歩進されることにより割込
み命令Bが発せられ、被検査プログツムPの次のアドレ
スAtの実行命令S3が取出され(LP8W命令によシ
)て、実行され、既述と同様に実行状態及び実行結果の
データが表示部8に表示される。
The data of condition code C, address counter IC), register 8 (execution results, etc.), and stack pointer SP are stored in memory 6 by 8AVB. Thereafter, the display control section 7 is activated by the control signal E, and the data D in the memory 6 is displayed on the display section 8. The inspector strives to discover errors by examining the displayed data. If there is no abnormality, when the keyboard 9 is operated, the start signal y is issued from the 1 display control section 7, which causes the tracer T to operate again and the interrupt command B to be issued by incrementing the counter 3. Then, the execution instruction S3 at the next address At of the program under test P is retrieved (by the LP8W instruction) and executed, and the execution state and execution result data are displayed on the display section 8 in the same way as described above. .

以上のように本発明は、被検査プログラムの1命令を実
行する毎に、その実行に関わるデータを表示部に表示せ
しめることによシブバッグを行いうるので、プログラム
の検査精度を向上しうる利点を有する。
As described above, the present invention has the advantage of improving the accuracy of program inspection, since it is possible to carry out a sive bag by displaying data related to the execution on the display every time one instruction of the program to be inspected is executed. have

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の一実施例を説明するブロックであシ、図
中に用いた符号は次の通りである。 1.6はメモリ、2は固定領域、3はカウンタ、4は割
込受付部、5は制御部、7は表示制御部、8は表示部、
9はキーボード、人、、ム1.Anはアドレス、BはI
IIJ込命令、Cはコンディジ冒ンコード、Dはデータ
、Eは制御信号、Fは起動信号、ICはアドレスカウン
タ、LP8WFi、四−ドF8W命令、R,R,はレジ
スタ、Sはスティタス情報、S皇 、8..8nは実行
命令、SPはスタックポインタ、BT社起動命令、Tは
トレーサを示す・
The drawings are blocks for explaining one embodiment of the present invention, and the symbols used in the drawings are as follows. 1.6 is a memory, 2 is a fixed area, 3 is a counter, 4 is an interrupt reception unit, 5 is a control unit, 7 is a display control unit, 8 is a display unit,
9 is the keyboard, person, 1. An is address, B is I
IIJ included instruction, C is a conditional code, D is data, E is a control signal, F is a start signal, IC is an address counter, LP8WFi, 4-do F8W instruction, R, R, is a register, S is status information, S Emperor, 8. .. 8n is the execution command, SP is the stack pointer, BT startup command, and T is the tracer.

Claims (1)

【特許請求の範囲】 処理装置と、メモリと、表示部とで構成され、被検査プ
ログラムを前記処理装置で実行させることにより、誤シ
を検査するプログラム検査方式におい度びに前記処理装
置の制御プマグラムに対し割込み命令を発する手段とを
備え、該割込み命令を受付けた前記処理装置が前記被検
査プログラムの1命令を実行したのち、該実行結果及び
実行状態のデータを前記メモリに格納し、該格納された
デー刈 りを前記表示メモリに格卵して表示せしめることKよシ
検査することを特徴とするプログラム検査方式。
[Claims] In the program inspection method, which includes a processing device, a memory, and a display unit, and which checks for errors by executing a program to be inspected by the processing device, each time a control program for the processing device is used. and means for issuing an interrupt instruction to the program, and after the processing device receives the interrupt instruction and executes one instruction of the program under test, the execution result and execution state data are stored in the memory; A program inspection method characterized in that the program inspection method is characterized in that the data obtained by the program is displayed in the display memory and then inspected.
JP56151674A 1981-09-25 1981-09-25 Program check system Pending JPS5852761A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56151674A JPS5852761A (en) 1981-09-25 1981-09-25 Program check system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56151674A JPS5852761A (en) 1981-09-25 1981-09-25 Program check system

Publications (1)

Publication Number Publication Date
JPS5852761A true JPS5852761A (en) 1983-03-29

Family

ID=15523760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56151674A Pending JPS5852761A (en) 1981-09-25 1981-09-25 Program check system

Country Status (1)

Country Link
JP (1) JPS5852761A (en)

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