JPS5852683Y2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS5852683Y2
JPS5852683Y2 JP1982132770U JP13277082U JPS5852683Y2 JP S5852683 Y2 JPS5852683 Y2 JP S5852683Y2 JP 1982132770 U JP1982132770 U JP 1982132770U JP 13277082 U JP13277082 U JP 13277082U JP S5852683 Y2 JPS5852683 Y2 JP S5852683Y2
Authority
JP
Japan
Prior art keywords
wire
thin metal
external lead
plating layer
nickel plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1982132770U
Other languages
Japanese (ja)
Other versions
JPS5889932U (en
Inventor
充典 島
博之 藤井
健一 立野
Original Assignee
松下電子工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電子工業株式会社 filed Critical 松下電子工業株式会社
Priority to JP1982132770U priority Critical patent/JPS5852683Y2/en
Publication of JPS5889932U publication Critical patent/JPS5889932U/en
Application granted granted Critical
Publication of JPS5852683Y2 publication Critical patent/JPS5852683Y2/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48455—Details of wedge bonds
    • H01L2224/48456—Shape
    • H01L2224/48458—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85385—Shape, e.g. interlocking features

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【考案の詳細な説明】 産業上の利用分野 本考案は、半導体装置の構成主体である半導体基板上の
電極を外部導出線へ接続する金属細線の、前記外部導出
線への接続点における接続強度を大幅に向上しうる構造
を具備する半導体装置に関するものである。[Detailed description of the invention] Industrial field of application The present invention is directed to improving the connection strength of thin metal wires that connect electrodes on a semiconductor substrate, which is the main component of a semiconductor device, to external lead wires at the connection point to the external lead wires. The present invention relates to a semiconductor device having a structure that can significantly improve performance.

従来例の構成とその問題点 トランジスタ、サイリスタあるいはダイオードなどの半
導体装置において、半導体素子の電極と外部導出線との
間の接続状態の良否は、半導体装置の特性あるいは信頼
性に大きな影響を及ぼす。Conventional configurations and their problems In semiconductor devices such as transistors, thyristors, and diodes, the quality of the connection between the electrode of the semiconductor element and the external lead-out line has a large effect on the characteristics or reliability of the semiconductor device.

すなわち、半導体装置の特性の改善あるいは信頼性の向
上をはかるためには、上述した半導体素子の電極と外部
導出線との間を接続するにあたり良好な接続状態をうろ
ことが大切である。That is, in order to improve the characteristics or reliability of a semiconductor device, it is important to ensure a good connection between the electrodes of the semiconductor element and the external lead wires.

ところで、半導体素子の電極は一般にアルミニウム膜で
形成され、また、この電極を外部導出線へ接続する金属
細線は一般に金線あるいはアルミニウム線である。Incidentally, the electrodes of semiconductor elements are generally formed of an aluminum film, and the thin metal wires that connect these electrodes to external leads are generally gold wires or aluminum wires.

そして、金属細線として金線を使用した場合、金とアル
ミニウムとは容易に合金化するため半導体素子上のアル
ミニウム電極に対して金線は強固に接続される。When a gold wire is used as the thin metal wire, the gold wire is firmly connected to the aluminum electrode on the semiconductor element because gold and aluminum are easily alloyed.

また、金属細線としてアルミニウム線を使用する場合に
は超音波法を駆使することによりアルミニウムよりなる
電極金属と金属細線とが一体物となる強固な接続状態が
得られる。Further, when an aluminum wire is used as the thin metal wire, by making full use of the ultrasonic method, a strong connection state in which the electrode metal made of aluminum and the thin metal wire are integrated can be obtained.

第１図は、金属細線による電極の外部導出線への接続ま
でが完了した電力用樹脂封止形トランジスタ組立体を示
す図であり、図中１はトランジスタ基板、２は放熱板を
兼ねる基板支持体、３は同基板支持体に繋るコレクタ用
の外部導出線、４および５はベースならびにエミッタ用
の外部導出線、６および７は外部導出線の金属細線接続
部そして８および９は金属細線である。Fig. 1 is a diagram showing a power resin-sealed transistor assembly in which the connection of electrodes to external lead wires using thin metal wires has been completed. In the figure, 1 is a transistor substrate, and 2 is a substrate support that also serves as a heat sink. 3 is an external lead wire for the collector connected to the substrate support, 4 and 5 are external lead wires for the base and emitter, 6 and 7 are thin metal wire connections of the external lead wires, and 8 and 9 are thin metal wires. It is.

第１図で示す組立構体では、上記のようにトランジスタ
基板１の電極金属層（図示せず）と金属細線８，９の材
質を選定するならば両者は強固に接着されるが、他方の
金属細線８および９と外部導出線の金属細線接続部６お
よび７との間の接続状態は必ずしも良好とはならない。In the assembled structure shown in FIG. 1, if the materials of the electrode metal layer (not shown) of the transistor substrate 1 and the thin metal wires 8 and 9 are selected as described above, they will be firmly bonded, but the other metal The connection state between the thin wires 8 and 9 and the metal thin wire connecting portions 6 and 7 of the external lead-out wires is not necessarily good.

すなわち、従来から金属細線と外部導出線１との間の接
続に関してはそれほど注意が払われていないことに加え
て、外部導出線４，５に対する表面処理は下地となる平
坦な金属にニッケル、銀あるいは金などのめっきを施す
のが一般的であった。In other words, in addition to conventionally not paying much attention to the connection between the thin metal wire and the external lead wire 1, the surface treatment of the external lead wires 4 and 5 was performed by applying nickel or silver to the flat metal base. Alternatively, it was common to use gold or other plating.

上記の金属中、金あるいは銀の貴金属めっき、とりわけ
金めつき膜を形成するものでは、このめっき膜の形成に
より半導体装置コストの大幅な高騰を招く。Among the above-mentioned metals, noble metal plating of gold or silver, particularly in the case where a gold plating film is formed, the formation of this plating film causes a significant increase in the cost of semiconductor devices.

また、銀あるいはニッケルのめつき膜を形成した場合、
これらと金属細線（金属あるいはアルミニウム線）とは
合金化せず、外部導出線と金属細線との接続は両者の機
械的なかみ合いによるところとなり、信頼性の面で不十
分であった。In addition, when a silver or nickel plating film is formed,
These and the thin metal wire (metal or aluminum wire) do not form an alloy, and the connection between the external lead wire and the thin metal wire depends on mechanical engagement between the two, which is insufficient in terms of reliability.

第２図は、金属細線と外部導出線との接続状態の一従来
例を示す断面図であり、図中、１０は外部導出線の下地
金属、１１はニッケルめっき層、１２は銀めっき層、そ
して１３は金属細線である。FIG. 2 is a sectional view showing a conventional example of a connection state between a thin metal wire and an external lead-out wire, and in the figure, 10 is a base metal of the external lead-out wire, 11 is a nickel plating layer, 12 is a silver plating layer, And 13 is a thin metal wire.

この図からも明らかなように、金属細線１３と銀めっき
層１２との間に合金反応は生じておらず、外部導出線と
金属細線１３との接着強度は下地金属に対するめつき層
の被着強度ならびにめっき層と金属細線とのかみ合いに
よる固着強度により定まっていた。As is clear from this figure, no alloy reaction occurs between the thin metal wire 13 and the silver plating layer 12, and the adhesive strength between the external lead wire and the thin metal wire 13 is determined by the adhesion of the plating layer to the base metal. It was determined by the strength and the adhesion strength due to the engagement between the plating layer and the thin metal wire.

このような問題に鑑みて、たとえば、めっき層を金にく
らべて安価なニッケルあるいは銀めっき層となすととも
にさらにこの上に金属細線となじみ易い金属を選択的に
設けること、あるいは金属細線と外部導出線との接触面
積を増すなどの方法も提案されている。In view of these problems, for example, the plating layer may be a nickel or silver plating layer, which is cheaper than gold, and a metal that is compatible with the thin metal wire may be selectively provided on top of the layer, or a metal that is compatible with the thin metal wire and externally drawn out. Other methods have also been proposed, such as increasing the contact area with the wire.

しかしながら前者では工数の増加によりやはりコストの
高騰を招き、また、後者では外部導出線の金属細線接続
部の面積の拡大に限度があり、さらに、金属細線の径を
太くする必要もあるためコストの高騰を招くなどの問題
がなお残されていた。However, in the former case, the cost increases due to the increase in man-hours, and in the latter case, there is a limit to the expansion of the area of the thin metal wire connection part of the external lead wire, and furthermore, it is necessary to increase the diameter of the thin metal wire, which reduces the cost. Problems such as rising prices still remained.

考案の目的 本考案は、以上説明してきた従来の半導体装置の金属細
線と外部導出線との間の接続に存在した問題を排除する
べくなされたものであり、安価な貴金属めっきを施すこ
となく強固な接続状態をうろことのできる構造の半導体
装置を提供するものである。Purpose of the invention The present invention was made in order to eliminate the problems that existed in the connection between the thin metal wire and the external lead wire of the conventional semiconductor device described above. The present invention provides a semiconductor device having a structure that allows flexible connection states.

考案の構成 本考案の半導体装置は、半導体基板上電極に一端が繋る
金属細線の他端が接続されるべき外部導出線の少くとも
金属細線接続部が前記外部導出線の下地金属を１〜１０
μｍ程度の粗さに粗面化し、この粗面に２〜５μｍのニ
ッケルめっき層を形成して、同ニッケルめっき層に前記
下地金属の粗さに応じた粗面状表面を備えたものである
。Structure of the Invention In the semiconductor device of the present invention, at least a thin metal wire connecting portion of an external lead wire to which one end is connected to an electrode on a semiconductor substrate and the other end of the thin metal wire is connected to a base metal of the external lead wire. 10
The surface is roughened to a roughness of about μm, a nickel plating layer of 2 to 5 μm is formed on this rough surface, and the nickel plating layer has a rough surface corresponding to the roughness of the base metal. .

本考案によると、外部導出線の金属細線接続部には、下
地金属の粗さに応じた粗面状態がニッケルめっき層の表
面にも形成されており、したがって、この上に金属細線
を圧着したとき、両者間に強固な接続性が確保される。According to the present invention, a rough surface condition corresponding to the roughness of the underlying metal is also formed on the surface of the nickel plating layer at the thin metal wire connection part of the external lead-out wire, and therefore, the thin metal wire is crimped onto the surface of the nickel plating layer. At this time, strong connectivity is ensured between the two.

実施例の説明 以下に第３図に参照して本考案の半導体装置について説
明する。DESCRIPTION OF EMBODIMENTS The semiconductor device of the present invention will be described below with reference to FIG.

本考案の半導体装置では、外部導出線の構造に特徴があ
り、外部導出線の金属細線接続部の表面に粗面化処理が
施されている。The semiconductor device of the present invention is characterized by the structure of the external lead-out wire, and the surface of the thin metal wire connection portion of the external lead-out wire is roughened.

なお、この粗面化処理は刻印法、化学エツチング法ある
いはサンドブラスト法などのいずれの方法によってもよ
いが、この加工を下地金属に施し、こののちニッケルめ
っき層を形成するとともにこの厚みを制御してニッケル
めっき層表面にも粗面化されたと同じ状態を残し、かく
して得られた金属細線接続部に金属細線の一端が接続さ
れている。Note that this surface roughening treatment may be performed by any method such as stamping, chemical etching, or sandblasting, but this process is applied to the base metal, and then a nickel plating layer is formed and the thickness is controlled. The same roughened state is left on the surface of the nickel plating layer, and one end of the thin metal wire is connected to the thin metal wire connection portion thus obtained.

第３図は、本考案の半導体装置の金属細線と外部導出線
との接続点の状態を示す断面図であり、１０は下地金属
である銅板、１１はニッケルめっき層、１３は金線そし
て１４は下地金属に形成された粗面化処理面である。FIG. 3 is a cross-sectional view showing the state of the connection point between the thin metal wire and the external lead wire of the semiconductor device of the present invention, in which 10 is a copper plate as a base metal, 11 is a nickel plating layer, 13 is a gold wire, and 14 is a roughened surface formed on the base metal.

本考案の半導体装置において大切なことは、ニッケルめ
っき層１１の表面にも下地金属１０に形成された凹凸が
あられれるよう下地金属１０への加工粗さに応じた厚さ
のニッケルめっき層を形成することである。What is important in the semiconductor device of the present invention is to form a nickel plating layer with a thickness that corresponds to the processing roughness of the base metal 10 so that the surface of the nickel plating layer 11 also has the unevenness formed on the base metal 10. It is to be.

因に、熱圧着法により金線を外部導出線へ接続するにあ
たり、金線の先端に形成される球状部分がニッケルめっ
き層に食い込み良好な接続状態を得ることのできるニッ
ケルめっき層表面の粗さく凹凸）は１〜１０μｍである
ことが判明した。Incidentally, when connecting a gold wire to an external lead wire using thermocompression bonding, the spherical part formed at the tip of the gold wire digs into the nickel plating layer, resulting in a good connection due to the roughness of the surface of the nickel plating layer. The roughness) was found to be 1 to 10 μm.

したがって、下地金属には少くとも１〜１０μｍ程度の
粗さの加工を施すことが必要である。Therefore, it is necessary to process the base metal to a roughness of at least about 1 to 10 μm.

また、下地金属に施された加工状態をニッケルめっき層
にも現出させるためには、ニッケルめっき層の厚みは５
μｍ以下とすることが必要である。In addition, in order to make the processed state applied to the base metal appear on the nickel plating layer, the thickness of the nickel plating layer should be 5.
It is necessary that the thickness be less than μm.

ただし、その厚みが２μｍ以下になると、下地金属がニ
ッケルめっき層中へ拡散し、ニッケルめっき層が変色す
る。However, if the thickness is less than 2 μm, the underlying metal will diffuse into the nickel plating layer, causing discoloration of the nickel plating layer.

したがって上記の加工条件の下におけるニッケルめっき
層の厚みは２〜５μｍであることが必要である。Therefore, the thickness of the nickel plating layer under the above processing conditions is required to be 2 to 5 μm.

また、かかるめつき膜厚の制御のためには無電解ニッケ
ル法よりも電解ニッケルめっき法を採用することがのぞ
ましい。Further, in order to control the thickness of the plating film, it is preferable to use an electrolytic nickel plating method rather than an electroless nickel method.

第４図は、本考案の半導体装置における金属細線の外部
導出線への接続状態と従来の半導体装置における接続状
態とを比較した実験結果を示す図である。FIG. 4 is a diagram showing the results of an experiment comparing the connection state of the thin metal wire to the external lead-out line in the semiconductor device of the present invention and the connection state in a conventional semiconductor device.

この実験は、銅を下地金属とし、この上にニッケルめっ
きを１〜３μｍ、さらにこの上に金めつきをＩＯμｍ施
してなる外部導出線に金線を接続した試料（例１：従米
構造）、銅を下地金属とし、この上にニッケルめっきを
５μｍ施してなる外部導出線にアルミニウム線を超音波
法により接続した試料（例２：従来構造）、銅を下地金
属とし、その表面に５μｍの粗さの粗面化処理を施し、
この上にニッケルめっき層を５μｍ施してなる外部導出
線に金線を熱圧着により接続した試料（例３：本考案構
造）ならびに金線をアルミニウム線にかえ、接続を超音
波法とする以外の条件を例３と同じにした試料（例４）
をそれぞれ１０ロツトずつ準備し、これらに２Ｗの電力
を５分間隔で５分間にわたり涜費させ、この状態を１０
００時間にわたり繰り返したのち、所定の引張力を金属
細線にかけることにより行った。In this experiment, a sample (Example 1: conventional structure) in which a gold wire was connected to an external lead wire made of copper as the base metal, 1 to 3 μm of nickel plating on this, and 10 μm of gold plating on top of this, A sample (Example 2: Conventional structure) in which an aluminum wire is connected by ultrasonic method to an external lead wire made of copper as a base metal and 5 μm of nickel plating applied thereon. The surface is roughened,
A sample in which a gold wire is connected by thermocompression bonding to an external lead wire formed by applying a nickel plating layer of 5 μm on this (Example 3: the structure of the present invention) and a sample in which the gold wire is replaced with an aluminum wire and the connection is made by ultrasonic method. Sample with the same conditions as Example 3 (Example 4)
Prepare 10 lots each, apply 2W of power to them for 5 minutes at 5-minute intervals, and maintain this condition for 10
After repeating the test for 00 hours, a predetermined tensile force was applied to the thin metal wire.

縦軸は断線発生率を示す。この結果から明らかなように
、下地基板上に高価な金めつきを施して熱圧着を行った
試料は引張力に対して弱く、本考案のごとく粗面化して
ニッケルめっきを施したものは接着強度がはるかに向上
した。The vertical axis indicates the occurrence rate of wire breakage. As is clear from these results, the samples that were thermocompressed with expensive gold plating on the base substrate were weak against tensile force, whereas the samples that were roughened and nickel plated as in the present invention were bonded. Strength is much improved.

また本考案は熱圧着法を用いて、工程上複雑である超音
波法を用いた場合とほぼ同等の接着強度を得ることがで
き、半導体装置の製造に格別の意義をもたらすことがで
きた。In addition, the present invention uses a thermocompression bonding method to obtain adhesive strength almost equivalent to that obtained using an ultrasonic method, which is complicated in terms of process, and brings special significance to the manufacturing of semiconductor devices.

すなわち、この第４図から明らかなように、従来は特に
金線をニッケルめっき層へ熱圧着した場合の断線発生率
が高かったが、本考案の半導体装置では、高価な貴金属
めっきを施すことなしに従来のような差を排除すること
ができ、また断線発生率も極めて低くなる。In other words, as is clear from Fig. 4, conventionally the incidence of disconnection was particularly high when a gold wire was thermocompression bonded to a nickel plating layer, but the semiconductor device of the present invention eliminates the need for expensive precious metal plating. It is possible to eliminate the difference seen in the conventional method, and the incidence of wire breakage is also extremely low.

なお、金線を熱圧着するにあたり、金線としてその先端
部の球状部の直径が３００μｍとなるものを用いた場合
、外部導出線上の凹凸の数を≧１０００／３００μｍφ
とすることにより特に良好な結果が得られた。In addition, when bonding the gold wire by thermocompression, when using a gold wire whose spherical part at the tip has a diameter of 300 μm, the number of unevenness on the external lead wire should be ≧1000/300 μmφ.
Particularly good results were obtained by using

考案の効果 以上の説明から明らかなように、本考案の半導体装置は
、粗面化された下地金属にこの粗面に応じた粗面状態表
面をもったニッケルめっき層を有するので、外部導出線
の金属細線接続部に対して高価な貴金属めっきを施すこ
となくこの金属細線接続部へ良好な状態で金属細線を接
続しうるものであり、半導体装置のコストの引き下げを
はかりつつその信頼性と特性を高めることができる。Effects of the Invention As is clear from the above explanation, the semiconductor device of the present invention has a nickel plating layer on a roughened base metal with a roughened surface corresponding to the roughened surface. The thin metal wire can be connected to the thin metal wire connection portion in good condition without applying expensive precious metal plating to the thin metal wire connection portion of the thin metal wire connection portion, and the reliability and characteristics of the thin metal wire connection portion can be reduced while reducing the cost of the semiconductor device. can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は電力用樹脂封止形トランジスタ組立構体を示す
斜視図、第２図は金属細線と外部導出線との接続部の状
態を示す断面図、第３図は本考案実施例半導体装置の金
属細線と外部導出線との接続部の状態を示す断面図、第
４図は従来の半導体装置と本考案実施例の半導体装置に
おける金属細線と外部導出線との接続部の接続強度の比
較実験の結果を示す図である。 １・・・・・・半導体基板、２・・・・・・基板支持体
、３，４．５・・・・・・外部導出線、６，７・・・・
・・金属細線接続部、１３・・・・・・金属細線、１０
・・・・・・外部導出線の下地金属、１１・・・・・・
ニッケルめっき層、１２・・・・・・銀めっき層、１４
・・・・・・粗面化処理面。FIG. 1 is a perspective view showing a power resin-sealed transistor assembly structure, FIG. 2 is a cross-sectional view showing the state of the connection between the thin metal wire and the external lead wire, and FIG. 3 is a diagram of the semiconductor device according to the embodiment of the present invention. A cross-sectional view showing the state of the connection between the thin metal wire and the external lead wire, and FIG. 4 is a comparison experiment of the connection strength of the connection between the thin metal wire and the external lead wire in the conventional semiconductor device and the semiconductor device of the embodiment of the present invention. FIG. 1... Semiconductor substrate, 2... Substrate support, 3, 4.5... External lead wire, 6, 7...
...Metal thin wire connection part, 13...Metal thin wire, 10
...Base metal of external lead wire, 11...
Nickel plating layer, 12...Silver plating layer, 14
...Roughened surface.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体基板上電極に一端が繋る金属細線の他端が接続さ
れるべき外部導出線の少くとも金属細線接続部が前記外
部導出線の下地金属を１〜１０μｍの粗さに粗面化した
粗面部と、この粗面部に２〜５μｍの厚さを有し、さら
に、同粗面部の粗さに応じた粗面状表面をもつニッケル
めっき層とで形成されていることを特徴とする半導体装
置。At least the thin metal wire connecting portion of the external lead wire, one end of which is connected to the electrode on the semiconductor substrate and the other end of the thin metal wire is to be connected, is formed by roughening the base metal of the external lead wire to a roughness of 1 to 10 μm. A semiconductor device comprising a surface portion and a nickel plating layer having a thickness of 2 to 5 μm on the rough surface portion and further having a rough surface according to the roughness of the rough surface portion. .
JP1982132770U 1982-08-31 1982-08-31 semiconductor equipment Expired JPS5852683Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982132770U JPS5852683Y2 (en) 1982-08-31 1982-08-31 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982132770U JPS5852683Y2 (en) 1982-08-31 1982-08-31 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS5889932U JPS5889932U (en) 1983-06-17
JPS5852683Y2 true JPS5852683Y2 (en) 1983-12-01

Family

ID=29926284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982132770U Expired JPS5852683Y2 (en) 1982-08-31 1982-08-31 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5852683Y2 (en)

Also Published As

Publication number Publication date
JPS5889932U (en) 1983-06-17

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