JPS5851639A - Word scanner system - Google Patents

Word scanner system

Info

Publication number
JPS5851639A
JPS5851639A JP15101881A JP15101881A JPS5851639A JP S5851639 A JPS5851639 A JP S5851639A JP 15101881 A JP15101881 A JP 15101881A JP 15101881 A JP15101881 A JP 15101881A JP S5851639 A JPS5851639 A JP S5851639A
Authority
JP
Japan
Prior art keywords
address
individual input
word
scanner
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15101881A
Other languages
Japanese (ja)
Other versions
JPS6322700B2 (en
Inventor
Takeo Sato
佐藤 武生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15101881A priority Critical patent/JPS5851639A/en
Publication of JPS5851639A publication Critical patent/JPS5851639A/en
Publication of JPS6322700B2 publication Critical patent/JPS6322700B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks
    • H04L12/40006Architecture of a communication node
    • H04L12/40032Details regarding a bus interface enhancer
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks
    • H04L12/40006Architecture of a communication node

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To cope with frequent extension of individual input sections without decreasing the transmission efficiency of a communication line, by providing a means omitting the transmission of data to the individual input section not returning a signal representing actual devices. CONSTITUTION:An individual input section 1-X and a word scanner 2'' are connected with a control signal bus 6 other than an address bus 4. When an address ADX is outputted, and when the individual input section 1-X assigned with the address ADX is mounted, a decoder 11 discriminates the address ADX transmitted from the bus 4 and outputs ''1'' and makes a gate 12 conductive. On the other hand, when the input section 1-X is not mounted, even if the address ADX is outputted from the scanner 2'' to the bus 4, no control signal CS is outputted to the bus 6. As a result, a gate 24 of the scanner 2'' is conductive, a clock signal CL immediately advances a step counter 21 by one step via gates 24 and 23 and outputs the next address.

Description

【発明の詳細な説明】 本発明はワードスキャナ一方式、特に複数の個別入力部
を走査するワードスキャナーを具備するサイクリックデ
ータ伝送方式におけるワードスキャナ一方式に関す。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a word scanner type, and more particularly to a word scanner type in a cyclic data transmission system comprising a word scanner scanning a plurality of individual input sections.

例えば多数の発電所・変電所等を含む給電系統を管理す
る給電指令所等において、各発電所ならびにf電断等の
運転状態を常時把握していることが不可欠となる。この
場合、各発電所才たは変電所から運転状態を示す諸デー
タを、給電指令所に伝送する手段として、サイクリック
データ伝送方式が広く適用される。
For example, in a power dispatch center or the like that manages a power supply system including a large number of power plants, substations, etc., it is essential to constantly know the operating status of each power plant and f-power outages. In this case, a cyclic data transmission method is widely applied as a means for transmitting various data indicating the operating status from each power plant or substation to the power dispatch center.

第1図は本発明の対象となるサイクリックデータ伝送方
式の系統例を示す図である。第1図において、例えば発
電所に設けられた送信装置10は、複数の個別入力部1
−1乃至1−N1ワードスキャナー2および伝送部3か
ら構成されている。各個別入力部1−1乃至1−Nは電
力・電圧等々の各データを所定のディジタル符号(以後
ワードW。
FIG. 1 is a diagram showing an example of a system of a cyclic data transmission system to which the present invention is applied. In FIG. 1, a transmitting device 10 installed in a power plant, for example, includes a plurality of individual input units 1
-1 to 1-N1 word scanner 2 and transmission section 3. Each individual input section 1-1 to 1-N inputs each data such as power and voltage into a predetermined digital code (hereinafter referred to as word W).

乃至WNと称T)に変換Tる。ワードスキャナー2は所
定の周期Tで総べての個別入力部1−1乃至1−Nを順
次走査し、対応するワードWI乃至WMを順次伝送部3
に伝達する。伝送部3は受領する各ワードW1乃至WN
を並列符号から直列符号lこ変換した後、所要の度胸を
加えて伝送路30に送出する。
to WN (T). The word scanner 2 sequentially scans all the individual input sections 1-1 to 1-N at a predetermined period T, and sequentially sends the corresponding words WI to WM to the transmission section 3.
to communicate. The transmitter 3 receives each word W1 to WN.
After converting the signal from a parallel code to a serial code, the signal is sent to the transmission line 30 with the necessary courage added.

第2図は従来あるワードスキャナ一方式の一例を示T図
である。第2図において、ステツプカウンタ21は一定
の間隔(以稜走査問隔tと称す)で入力される歩進信号
8Uを計数し、各計数出力をアドレスAD、乃至AD、
としてアドレスバス4を介して各個別入力51−1乃至
1−Nlこ伝送する。各個別入力部1−X(Xは1乃至
N)はアドレスバス4,0)ら受領するアドレスAD、
乃至AD。
FIG. 2 is a T diagram showing an example of a conventional word scanner of one type. In FIG. 2, a step counter 21 counts step signals 8U input at fixed intervals (hereinafter referred to as edge scanning interval t), and outputs each count from addresses AD to AD,
The respective individual inputs 51-1 to 1-N1 are transmitted via the address bus 4 as follows. Each individual input section 1-X (X is 1 to N) receives an address AD from the address bus 4,0);
to AD.

が自己に割当てられているアドレスADxと一致した走
査間隔tに、保持しているワードWxをデータバス5を
介して伝送部3に伝送する。ステップカウンタ21は最
終アドレスAD、を出力し終ると、リセット信号)t8
が入力されてリセットされる橡配線されており、再び先
頭アドレスAD1から順次針数出力を繰返す・ 以上の説明から明らかな如く、従来あるワードス中ヤナ
一方式は、一定の走査問隔鬼でアドレスAD、乃至AD
いを順次アドレスバス4に送出する。
transmits the held word Wx to the transmission unit 3 via the data bus 5 at a scanning interval t that coincides with the address ADx assigned to itself. When the step counter 21 finishes outputting the final address AD, a reset signal) t8
is input and reset, and the number of stitches is output again sequentially from the first address AD1. As is clear from the above explanation, the conventional one-way word processing system outputs the address at a constant scanning interval. AD, to AD
The addresses are sequentially sent to the address bus 4.

然し個別入力部1−1乃至1−Nは最初から全部実装さ
れることは寧ろ稀で、例えば発電所設備の拡充に伴ない
順次増設されることが多い。令弟2図において、個所人
力部1−Jおよび1−Kか実装されてないとすると、か
−る場合にも従来あるワードスキャナー2は、未実装個
別入力部1.−Jおよび1−Kに割当てられているアド
レスAD。
However, it is rare that all of the individual input units 1-1 to 1-N are installed from the beginning, and they are often added sequentially as power plant equipment is expanded, for example. In Figure 2, if the individual input units 1-J and 1-K are not implemented, the conventional word scanner 2 will also have the unimplemented individual input units 1. Address AD assigned to -J and 1-K.

およびADKをそれぞれ走査間隔を宛アドレスノ(スに
送出する。当然、未実装個別入力部1−Jおよび1−K
に相当するワードW□およびW工は出力されないので、
伝送部3がデータ/(ス5から走査周期Tで受領するワ
ード列(こは、第3図(こ示す如き遊体間隔が生じ、延
いては通信路30の伝送効率を低下せしめる。か−る従
来あるワードスキャナ一方式の欠点を除去する目的で、
第4図に示す如きワードスキャナ一方式が既に試みられ
ている。第4図に示されるワードスキャナー2′は、ス
テップカウンタ21の計数出力が読取り専用メモリ22
により、実装済み個別入力1部1−1乃至1−(J−1
)および1−(K+1、)乃至1−Nに対応するアドレ
スAD、乃至AD□−8およびADK+、乃至ADHに
変換された後、アドレスバス4に伝送される。その結果
、アドレス/(ス4には未実装個別入力部1−Jおよび
1−Kに割当てられているアドレスAD、およびADI
Lは伝達されず、従ってデータバス5を経由して伝送部
3に伝達されるワード列は、第5図に示される如く遊体
間隔を含まぬ状態となり、走査周期T′も短縮され、通
信路30の伝送効率も向上する。然し個別入力部が噺次
増般される度醗こ、断取り専用メモリ22のアドレス変
換機能も変更されねばならぬ。
and ADK respectively to the destination address No. 1-J and 1-K.
Since the words W□ and W engineering corresponding to are not output,
When the transmission unit 3 receives the word string (which is received from the data/(s) 5 at the scanning period T), an idle interval as shown in FIG. In order to eliminate the drawbacks of conventional word scanners,
One type of word scanner as shown in FIG. 4 has already been tried. The word scanner 2' shown in FIG.
Accordingly, the installed individual input section 1 1-1 to 1-(J-1
) and 1-(K+1, ) to 1-N, and are converted into addresses AD, to AD□-8, and ADK+, to ADH, and then transmitted to the address bus 4. As a result, address /
L is not transmitted, and therefore, the word string transmitted to the transmission unit 3 via the data bus 5 does not include any idle intervals as shown in FIG. 5, and the scanning period T' is also shortened, and the communication The transmission efficiency of the line 30 is also improved. However, as the number of individual input units increases, the address conversion function of the memory 22 dedicated to cutting must also be changed.

al12堆り専用メモリ22のアドレス変換機能はプロ
グラムにより設定されているが、該プログラムの変更は
製造元以外で爽施するのは極めて困難であるため、所俵
変更期間も長(なり、個別入力部の増設が頻繁に行われ
る場合には不適当である。
The address conversion function of the memory 22 dedicated to al12 stacking is set by a program, but it is extremely difficult to change the program by anyone other than the manufacturer, so the period for changing the bales is long (and the individual input section is not required). It is unsuitable if the number of units is frequently increased.

本発明の目的は、前述の如き従来あるワードス中ヤナ一
方式の欠点を除去し、通信路の伝送効率を低下させず、
且つ個別入力部の頻繁な増設にも対処可能なワードスキ
ャナ一方式の実現に在る。
The purpose of the present invention is to eliminate the drawbacks of the conventional one-way communication system as described above, and to avoid reducing the transmission efficiency of the communication channel.
Moreover, it is possible to realize a one-type word scanner that can cope with the frequent addition of individual input units.

この目的は、複数の個別入力部を走査するワードスキャ
ナーを具備するサイクリックデータ伝送方式において、
前記個別入力部を走査するワードスキャナーから走査さ
れた時に実装を示す信号を返送する手段を設け、前記ワ
ード、スキャナーには前記実装置を示す信号を返送しな
い個別入力部に対Tるデータの伝送を省略する手段を設
けることにより達成される・ 以下、本発明の一実施例を第6図および第7図により説
明する。第6図は、本発明の一実施例によるワードスキ
ャナ一方式を適用した送信装置の構成を示す図、第7図
は本発明の一実施例着こよるワードス中ヤナ一方式を示
す図である。なお全図を通じて、同一符号は同一対象を
示T0第6鮪において、個別入力部1−1′乃至1−N
′とワードスキャナー2#とは、アドレスバス4以外に
制御信号パス6によっても接続されている。該制御信号
バス6はワードスキャナー2′からアドレスバス4を経
由して自己に割当てられたアドレスADx、¥e受領し
た個別入力部1−X′が、実装されていることを示す信
号(以後制御信号08と称T)をワードスキャナー21
に返送Tるため−こ使用される。各個別入力部1−1乃
至1−N1こは第7図に示される如く、制御信号O8を
出力するためのゲート12およびトランジスタ13が設
けられている。またワードスキャナー2′には第7図番
こ示される如く、制御信号バス6から受領する制御信号
C8iこより制御されるクロック信号OLを、歩信信号
SU4ζ加えてステップカウンタ21に入力するゲート
23および24が設けられており、第4図に示される如
き斂取り専用メモリ22は使用されない。第7図におい
て、ワードスキャナー2′のステップカウンタ21は通
常走査間隔tでゲート23を介して入力される歩進信号
SUを計数し、アドレスADI乃至ADNを拳法アドレ
スバス44こ出力する。今アドレスADKか出力された
時に、該アドレスADxを割当てられた個別入力部1−
Xが実装されていれば、デコーダ11がアドレスバス4
から伝送されるアドレスADxを識別して論塩値1を出
力し、ゲート12を導通状態とする0その結果、導通状
態となりたゲート12を介して電圧Vがトランジスタ1
3を付勢し、鹸埋値0の制御信号08を制御信号バス6
に出力させる。該制御信号O8は制御信号バス6を介し
てワードスキャナー2’lこ伝送され、ゲート24を阻
止状態とする。その結果、クロックOLはステップカウ
ンタ21に入力されることは無く、個別入力部1−Xに
所定の走査間隔を内に保持するワードをデータバス5を
介して伝送部3に伝達する。
This purpose is achieved in a cyclic data transmission system equipped with a word scanner that scans a plurality of individual input sections.
A means is provided for returning a signal indicating implementation when scanned by a word scanner that scans the individual input section, and transmitting data to the individual input section that does not return a signal indicating the actual device to the word scanner. This is achieved by providing means for omitting the following. An embodiment of the present invention will be described below with reference to FIGS. 6 and 7. FIG. 6 is a diagram showing the configuration of a transmitter to which a word scanner type is applied according to an embodiment of the present invention, and FIG. 7 is a diagram showing a one-type word scanner type according to an embodiment of the present invention. . In addition, throughout the figures, the same reference numerals indicate the same objects.In the T0 6th tuna, individual input units 1-1' to 1-N
' and word scanner 2# are connected not only by address bus 4 but also by control signal path 6. The control signal bus 6 receives a signal (hereinafter a control Signal 08 (T) is word scanner 21
This is used to return the item to the customer. As shown in FIG. 7, each individual input section 1-1 to 1-N1 is provided with a gate 12 and a transistor 13 for outputting a control signal O8. Further, as shown in FIG. 7, the word scanner 2' has a gate 23 which inputs a clock signal OL controlled by a control signal C8i received from a control signal bus 6 to a step counter 21 in addition to a step signal SU4ζ. 24 is provided, and the memory 22 dedicated to balance collection as shown in FIG. 4 is not used. In FIG. 7, the step counter 21 of the word scanner 2' counts the step signal SU inputted through the gate 23 at the normal scanning interval t, and outputs addresses ADI to ADN to the Kenpo address bus 44. When the address ADK is output now, the individual input section 1- to which the address ADx is assigned
If X is implemented, the decoder 11 uses the address bus 4
It identifies the address ADx transmitted from the transistor 1 and outputs the logic value 1, and makes the gate 12 conductive.As a result, the voltage V is applied to the transistor 1 through the gate 12, which has become conductive.
3 is activated, and the control signal 08 with the embedded value 0 is sent to the control signal bus 6.
Output to . The control signal O8 is transmitted to the word scanner 2' via the control signal bus 6 and places the gate 24 in a blocked state. As a result, the clock OL is not input to the step counter 21, and the words that keep the predetermined scanning interval within the individual input section 1-X are transmitted to the transmission section 3 via the data bus 5.

一方個別入力部1−Xが実装されていなかった場合には
、ワードスキャナー2′からアドレスノくス4にアドレ
スADtψS出力尊れても、制御信号バス6に制御信号
O8が出力されることは無い。その結果、ワードスキャ
ナー2′のゲート24は導通状態となり、クロック信号
OLがゲート24および23を介してステップカウンタ
21を直ちに一歩進させ、次のアドレスADx+1を出
力させる。
On the other hand, if the individual input section 1-X is not installed, even if the address ADtψS is output from the word scanner 2' to the address node 4, the control signal O8 will not be output to the control signal bus 6. None. As a result, the gate 24 of the word scanner 2' becomes conductive, and the clock signal OL immediately increments the step counter 21 by one step via the gates 24 and 23 to output the next address ADx+1.

このaSこしてワードスキャナー2′に未実装の個別入
力部に対しては所定の走査間隔tを資すこと無く走査を
進める。ステップカウンタ21は最終アドレスAD、を
出力し終ると、リセット信号R8によりリセットされ、
再び先頭アドレスAD、から順次出力を繰返T。
As a result of this aS, scanning proceeds without using the predetermined scanning interval t for individual input units that are not mounted on the word scanner 2'. When the step counter 21 finishes outputting the final address AD, it is reset by a reset signal R8,
Repeat T to output sequentially from the first address AD again.

以上の説明から明らかな如く、本実施例1こよnば、ワ
ードスキャナー2′は未実装の個別入力部に対しては所
定の走査間隔tを費Tこと無く走査を進めるので、デー
タバス5を経由して伝送部3に伝達されるワード列は、
略々第5図に勢しい遊体間隔を含まぬ状態となる。従っ
て例えば発電所設備の増設に伴ない、給電指令所等に伝
送部べき緒データが増加した場合にも、対応する個別入
力部1−Xを増設するのみで、ワードスキャナー2#に
は訳出し専用メモリのプログラム費更の如き複雑な改変
作業は不要となる。
As is clear from the above description, according to the first embodiment, the word scanner 2' scans unmounted individual input sections without spending the predetermined scanning interval t, so the data bus 5 is The word string transmitted to the transmission unit 3 via
The state is approximately as shown in FIG. 5, which does not include the large free-width spacing. Therefore, even if, for example, the transmission unit code data increases at the power dispatch center etc. due to the expansion of power plant equipment, all you need to do is add the corresponding individual input unit 1-X, and the translation will be sent to Word Scanner 2#. There is no need for complex modification work such as changing the program cost of a dedicated memory.

なお、第6&IJおよび第7図はあく迄本発明の一実施
例に過ぎず、例えば個別入力部l−Xの制御信号08出
力手段、並びにワードスキャナー2′の走査繰上げ手段
は図示されるものに限定されることは無く、他−こ幾多
の変形が考慮されるが、何れの場合にも本発明の効果は
変らない。また、本発明の対象は発電所igc電所電断
a′Mi令所造の間のブール伝送方式に限定6れぬtと
は言う迄もない。
Note that FIGS. 6 & IJ and FIG. 7 are only one embodiment of the present invention, and for example, the control signal 08 output means of the individual input section l-X and the scanning advance means of the word scanner 2' are as shown in the figures. There are no limitations and many other modifications may be considered, but the effects of the present invention remain the same in either case. It goes without saying that the object of the present invention is not limited to the Boolean transmission system between power plants, IGC, and power plants.

以上、本発明によれば、前記サイクリックデータ伝送方
式において、通信路の伝送効率を低下させるととの無か
、且つ個別入力部、の頻繁な増設に充分即応可能なワー
ドスキャナ一方式が実現可能となる。
As described above, according to the present invention, in the cyclic data transmission method, a single word scanner type is realized which does not reduce the transmission efficiency of the communication path and can sufficiently respond quickly to the frequent addition of individual input units. It becomes possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の対象となるサイクリックデータ伝送方
式の系統例を示す図、第2図は従来あるワードスキャナ
一方式の一例を示す図、第3図は第2図におけるワード
列の一例を示す図、第4図は従来あるワードスキャナ一
方式の他の一例を示す図、第5図は第4図番こおけるワ
ード列の一例を示す図、第6図は本発明の一実施例によ
るワードスキャナ一方式を適用した送信装置の構成を示
す図、第7図は本発明の一実施例奢こよるワードスキャ
ナ一方式を示す図である。 図において、10は送信装置、20は受信装置、30は
通信路、1−1乃至1−N、1−1’乃至1−N’ 、
1−(J−1)% l−J、 1−に、 1−(K+1
)およびi−xは個別入力部、2.2′および2#はワ
ードスキャナー、3は伝送部、4はアドレスバス、5は
データバス、6は制御信号パス、11はデコーダ、12
.23および24はゲート、13はトランジスタ、21
はステップカウンタ、22は紋取り専用メモリ、SUは
歩進信号、AD、乃至AD、、AD、0、ADK+1お
よびADxはアト′スーWl乃至wN、 w、l、 W
、 、 W、 、 WK十。 およびWxはワード、TおよびT′は走査周期、ttは
走置間隔、R8はリセット信号、O8は制御信号、OL
はりpツク信号を示す。 箒1図 気 2− 図 ? ヲ  后 矛 4  固 fb図 予 7 図
FIG. 1 is a diagram showing an example of a system of a cyclic data transmission system to which the present invention is applied, FIG. 2 is a diagram showing an example of a conventional word scanner type, and FIG. 3 is an example of the word string in FIG. 2. FIG. 4 is a diagram showing another example of the conventional one-sided word scanner. FIG. 5 is a diagram showing an example of the word string in FIG. 4. FIG. 6 is an embodiment of the present invention. FIG. 7 is a diagram showing the configuration of a transmitting device to which a single word scanner type is applied, and FIG. 7 is a diagram showing a single word scanner type according to an embodiment of the present invention. In the figure, 10 is a transmitting device, 20 is a receiving device, 30 is a communication path, 1-1 to 1-N, 1-1' to 1-N',
1-(J-1)% l-J, 1-to, 1-(K+1
) and i-x are individual input sections, 2.2' and 2# are word scanners, 3 is a transmission section, 4 is an address bus, 5 is a data bus, 6 is a control signal path, 11 is a decoder, 12
.. 23 and 24 are gates, 13 is a transistor, 21
is a step counter, 22 is a memory dedicated to pattern capture, SU is a step signal, AD, 0, ADK+1 and ADx are at'su Wl to wN, w, l, W
, , W, , WK ten. and Wx is word, T and T' are scanning period, tt is scanning interval, R8 is reset signal, O8 is control signal, OL
The beam indicates a p-took signal. Houki 1 diagram 2- diagram? wo back spear 4 hard fb diagram 7 figure

Claims (1)

【特許請求の範囲】[Claims] 被数の個別入力部を走をするワードスキャナーを具備す
るサイクリックデータ伝送方式において、前記個別入力
部には前記ワードスキャナーから走査された時に実装を
示す信号を返送する手段を設置け、前記ワードスキャナ
ーには前記実装を示す信号を返送しない個別入力部に対
Tるデータの伝送を省略する手段を設けることを特徴と
するワードスキャナ一方式。
In a cyclic data transmission method comprising a word scanner that scans individual input sections of a decimal number, the individual input section is provided with means for returning a signal indicating implementation when scanned by the word scanner; A word scanner of one type, characterized in that the scanner is provided with means for omitting data transmission to the individual input section that does not return a signal indicating the implementation.
JP15101881A 1981-09-24 1981-09-24 Word scanner system Granted JPS5851639A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15101881A JPS5851639A (en) 1981-09-24 1981-09-24 Word scanner system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15101881A JPS5851639A (en) 1981-09-24 1981-09-24 Word scanner system

Publications (2)

Publication Number Publication Date
JPS5851639A true JPS5851639A (en) 1983-03-26
JPS6322700B2 JPS6322700B2 (en) 1988-05-12

Family

ID=15509493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15101881A Granted JPS5851639A (en) 1981-09-24 1981-09-24 Word scanner system

Country Status (1)

Country Link
JP (1) JPS5851639A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60183836A (en) * 1984-03-02 1985-09-19 Oki Electric Ind Co Ltd Time division multiplexing device
JPS63209339A (en) * 1987-02-26 1988-08-30 Nec Corp Cyclic digital information transmitter

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51108565A (en) * 1975-02-08 1976-09-25 Hitachi Ltd ANAROGUNYURYOKUSEIGYOHOSHIKI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51108565A (en) * 1975-02-08 1976-09-25 Hitachi Ltd ANAROGUNYURYOKUSEIGYOHOSHIKI

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60183836A (en) * 1984-03-02 1985-09-19 Oki Electric Ind Co Ltd Time division multiplexing device
JPS63209339A (en) * 1987-02-26 1988-08-30 Nec Corp Cyclic digital information transmitter

Also Published As

Publication number Publication date
JPS6322700B2 (en) 1988-05-12

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