JPS5850648Y2 - Priority selection circuit - Google Patents

Description

[Detailed description of the invention] This invention relates to an improvement of the invention "priority selection circuit" which was previously applied for a patent by the same applicant as the present invention.
The purpose is to simplify the level detection means in the circuit.

When the on-board receiving system of each device such as automatic train control (abbreviated as ATC) or automatic train stop (abbreviated as ATS) receives multiple pieces of speed control information from the ground at the same time, the lowest (lowest speed) one of them is received. A lower speed priority selection circuit is adopted that outputs the speed to the control system.

Conventionally, this type of selection circuit has been comprised of an electromagnetic relay and its contact circuit.

The priority selection circuit of the above application is a non-contact priority selection circuit in place of an electromagnetic relay, and an example of the circuit configuration is shown in FIG.

That is, in the figure, emitter-grounded transistor saturation amplification circuits are connected in multiple stages corresponding to the number of set speed information, an input terminal is provided at the connection point of each stage, and a level detection circuit is installed in the collector circuit of each stage. A Trl is a device that connects a circuit and obtains output information from its detection output.

T r 2 t T r 3 t...Trn are the amplifier transistors of each stage, CDI, CD2, C
D3, . . . CDn are backflow prevention diodes inserted in the collector circuit of each transistor, DI1,
DI2゜−DI n is input information IP1, IF5,
=・Reverse current blocking diode, LDl, inserted in each input circuit of IPn and connected to the connection point of each stage.
.

LD2, . . . LDn are AC level detection circuits connected to the collector output circuits of each stage via DC blocking capacitors CI, C2, . . . Cn, respectively, and CP is the base of the transistor Trl of the first stage amplifier circuit. A square wave alternating current generator connected to a circuit that generates a square wave alternating current signal cp
occurs.

A voltage (g) VCC is constantly applied to the collector circuit of each stage above.
is supplied, and the input information IP1, I
When there is no information on F5, . . . IPn, each stage operates by switching the square wave alternating current signal cp.

However, at that output level, the level detection circuits LD1, L
D2, . . . , the operating bell of each detection circuit is set so that no output is generated from LDn.

On the other hand, the input voltage level of the information IP1tIP2, . Circuit L
Drive D1 and output information UP corresponding to input information IP1
Output I.

At this time, the transistor Tr2 in the subsequent stage is saturated by the DC voltage of the input information IP1, so if the information IP1,
Even if the IF5 inputs the information simultaneously, the output information UP2 corresponding to the upper input information IP2 is not outputted, and the lower information UPI is outputted preferentially.

The above is an outline of the embodiment related to the invention of the above patent application, and the level detection circuits LD1tLD2, . . . in FIG.
When implementing LDn with a known circuit, it is optimal to use a Schmitt circuit as shown in FIG.

However, if a Schmitt circuit as shown in the figure is used to construct a non-contact lower speed priority circuit, the disadvantage is that the number of circuit components increases, making the circuit complex and large.

In view of the above points, the present invention simplifies this type of priority selection circuit by configuring a level detection circuit as shown in FIG.

An embodiment of the present invention will be described below with reference to FIG. 3. In the figure, the circuits to which the power supply voltage vCCl is applied are the level detection circuits LD1 and LD2 of FIG. 1.

...It is a circuit that is almost the same as the circuit excluding the output circuit including LDn etc., and the transistors and diodes of each stage are also
Indicated by the same symbols as in the figure.

As shown in FIG. 3, the present invention includes transistors Tra1, tTra2, tTra3-T in each stage of the circuit.
A common emitter saturation amplification circuit such as RAN is provided, and the emitter of each transistor is connected to the power supply voltage (T) as shown in the figure.
It is connected to the VCCI circuit, and (g) a power supply voltage (g) VCC2 higher than Vccl is supplied to the collector of each transistor via a resistor.

Further, the base of each transistor is connected to another transistor in each stage, for example, the base of transistor Tra1 is connected to the collector of transistor Tr1 via a resistor.

Capacitors Ca1, Ca2 tca3, ""
Can is a DC blocking capacitor provided in the output circuit of each stage.

The operation of the level detection circuit according to the present invention will be explained using the circuit surrounded by the two-dot chain line in Fig. 3 as a representative example.
If 1 is not present, the base voltage of the transistor Tra1 is lower than the emitter voltage connected to the power supply voltage (VCCl) circuit, so the transistor Tra1 is turned off.
state is maintained and no output UPI is generated.

Next, the DC voltage of input information IP1 is the already mentioned power supply voltage Vc
As in the case of c, when the voltage is set sufficiently higher than the voltage vCC1, when the information IPI is input, the transistor Tr1, which is switching with the square wave signal cp, is turned off.
At time 2, the base voltage of transistor Tra1 becomes higher than its emitter voltage, so transistor Tra1 is turned on.
becomes.

When the transistor Tr1 is turned on, the base voltage of the transistor Tra1 becomes lower than its emitter voltage, and the transistor Tra1 is turned off.

Therefore, when there is an input IP1, an AC output UPI synchronized with the square wave signal cp is obtained from the output circuit of the transistor Tra1.

Of course, the above operation is the same in the circuits of other stages.

When the circuit shown in the embodiment shown in FIG. 3 is used as a speed signal selection circuit from lower to upper stages in order from the previous stage to the latter stage, the circuit becomes a lower speed priority circuit, which is the same as the invention of the above patent application. Safety is not compromised either.

In addition, the level detection circuit of the present invention is extremely simplified compared to the Schmitt circuit shown in Figure 2, and requires only a small circuit volume, resulting in significant economical and man-hour savings. be.

[Brief explanation of drawings]

Fig. 1 shows an embodiment of the earlier patent application "Priority Selection Circuit", Fig. 2 shows a known Schmitt circuit diagram which is a level detection circuit of the same circuit, and Fig. 3 shows an embodiment of the priority selection circuit of the present invention. It is a circuit diagram. cp...square wave alternating current generator, Tr1tTr2tTr3
,...Trn=-) transistor, Tral. Tra2tTra3t=Tran-transistor, IP
I, IF5, -IPn=input information, UPI. UF4, UF3,...UPn...Output information.

Claims (1)

[Scope of utility model registration request] A common-emitter transistor saturation amplification circuit driven by an AC wave signal is connected in multiple stages corresponding to the number of information to be input at a level higher than the supply voltage that is constantly applied to the circuit, and is placed at a position corresponding to the connection point of each stage. Input circuits for the corresponding information are respectively provided, and an AC level detection circuit connected to the collector circuit of each stage is provided to correspond to the input information of each stage,
In addition, in a priority selection circuit that generates an output from the level detection circuit with priority given to the information input to the previous stage, a transistor saturation amplification circuit different from the one described above is additionally installed in each of the stages, and the emitter side of the additional circuit is connected to the one described above. In the supply voltage circuit, a level detection circuit is configured such that the base side is connected to the collector of the installed base transistor, and the voltage applied to the auxiliary circuit is set at a higher level than the supply voltage to extract output information. Features a priority selection circuit.