JPH0213513B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical deflection circuit for a television receiver or the like which is suitable for integrated circuit (IC).

A vertical deflection system implemented as an IC is generally composed of two ICs: an IC containing a vertical oscillation circuit and a vertical deflection drive circuit, and an IC for the vertical deflection output circuit, taking into account voltage and thermal issues. be. Further, when the vertical deflection output circuit is configured with an IC, a power supply pump-up method that increases the voltage supplied to the vertical deflection output circuit during the vertical retrace period is a suitable circuit method for power saving.

FIG. 1 is a block diagram of a power supply pump-up type vertical deflection output circuit. In Figure 1, 1
2 is a vertical deflection drive circuit, 2 is a vertical deflection output circuit, 3 is a power supply pump-up circuit, 4 is a DC and AC feedback circuit, 5 is a power supply pump-up capacitor, 6 is a diode, and 7 is a vertical deflection yoke. In the case of this figure, the vertical deflection output circuit 2 is an inverting amplifier. The dotted line in the figure is the IC for the vertical deflection output circuit on the right side and the IC containing the vertical deflection drive circuit on the left side.
Indicates the boundary between

During the scanning period, the connection point b1 is grounded by the power supply pump-up circuit 3, and the capacitor 5 is charged up to the power supply voltage Vcc supplied to the power supply terminal 10. During the retrace period, the power supply pump-up circuit 3 connects the connection point b1 to the power supply voltage Vcc. Therefore, the voltage supplied to the vertical deflection output circuit 2 is approximately twice the power supply voltage Vcc, and the diode 6 is cut off. The operation of the power supply pump-up circuit 3 during the scanning period and blanking period is triggered by the pump-up trigger pulse generated by the vertical oscillation circuit and supplied from the terminal 11, and the connection point b
2 exceeds the power supply voltage Vcc by the power supply pump-up circuit 3.

FIGS. 2A and 2B show the input voltage waveform and output voltage waveform of the vertical deflection output circuit, respectively, FIG. 2C shows the current waveform flowing through the vertical deflection yoke, and D shows the pump-up trigger pulse waveform. Further, T _R and T _S are a vertical blanking period and a vertical scanning period, respectively.

FIG. 3 is an example of an actual circuit corresponding to the block diagram of FIG. Overlapping parts are indicated by the same reference numerals. At the connection points b ₃ and b ₄ of the vertical oscillation circuit 50,
A vertical sawtooth wave and a pump-up trigger pulse are output respectively. The vertical deflection circuit 2 consists of a single-ended push-pull circuit consisting of transistors Q ₁ to _{Q 4} , and the power supply pump up circuit 3 consists of transistors Q ₅ to _{Q 10} and is connected to a terminal 11 .
controlled by a trigger pulse applied to the Further, D ₂ and D ₃ are clamp diodes.

The deflection yoke 7 is driven by the transistor Q ₃ in the first half of the vertical scanning period and by the transistor Q ₄ in the second half. In this vertical scanning period, the transistor
Since Q ₅ and Q ₉ are off, the connection point b ₁ is grounded and the capacitor 5 is charged to the power supply voltage Vcc.

During the retrace period, connection point b ₄ is connected from the vertical oscillation circuit 50.
A positive pump-up trigger pulse is output to
Since transistors Q ₅ and Q ₉ are turned on, transistors Q ₄ and Q ₁₀ are turned off. During the first half of the retrace period, due to the retrace pulse generated in the deflection yoke 7, the current in the deflection yoke 7 flows to the power source through the diode D ₂ , the capacitor 5, and the diode D ₃ . At this time, since the connection point _b2 exceeds the power supply voltage Vcc, transistors _Q6 , _Q7 , and _Q8 are turned on. Therefore,
The voltage supplied to the vertical deflection output circuit 2 is approximately twice the power supply voltage Vcc. In the latter half of the retrace period, the current in the deflection yoke 7 flows through the transistor Q ₈ , the capacitor 5,
Flows through transistor _Q3 . transistor
_Q5 protects transistor _Q4 by cutting off transistor _Q4 during retrace.

By the way, in such a method, the vertical oscillator 50
Since the trigger pulse for pumping up must be created using the vertical oscillator 50, the configuration of the vertical oscillator 50 is limited. Furthermore, when integrated into an IC, a terminal 11 dedicated to the pump-up trigger pulse is required for both the IC for the vertical deflection output circuit 2 and the IC including the vertical oscillation circuit 50 and the vertical deflection drive circuit 1. Also, this type of vertical deflection output IC cannot be connected to a circuit that does not have a pump-up trigger pulse output.

An object of the present invention is to provide a vertical deflection circuit that facilitates the design of the vertical oscillation circuit and allows the number of terminals to be reduced for integration.

In the present invention, by detecting the voltage at the output terminal of the vertical deflection output circuit as described above, a reference potential is applied to one end of the power supply pump-up capacitor during the vertical scanning period, and a power supply potential is applied to one end of the capacitor during the vertical retrace period. For a vertical deflection circuit equipped with a power supply pump-up circuit that gives A trigger pulse control circuit is provided which disconnects one end of the capacitor from the reference potential point at the output.Furthermore, the vertical deflection output circuit has a base connected to an input terminal to which the input signal is applied, and an emitter connected to the input terminal via a resistor. a transistor connected to a reference potential point, means for biasing the emitter of the transistor by supplying current to the resistor, and means for driving the vertical deflection coil in response to the collector output of the transistor; The trigger pulse control circuit is characterized in that it has a transistor whose base is connected to the input terminal and whose emitter is directly connected to a reference potential point, and the detection output is obtained from the collector of this transistor.

In this way, a terminal dedicated to the trigger pulse is not required, and the configurations of both the input stages of the vertical deflection output circuit and the trigger pulse control circuit are simplified and optimal for integration into integrated circuits.

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 4 is a block diagram showing one embodiment of the present invention, and parts that overlap with those in FIG. 1 are designated by the same reference numerals. That is, the vertical oscillation circuit 50 in FIG.
It has a negative pulse detection circuit 8 which detects a negative pulse of the output of the vertical deflection drive circuit 1 instead of the trigger pulse from the vertical deflection drive circuit 1, and this negative pulse detection circuit 8 generates a pump-up trigger pulse.
FIG. 5A shows the input voltage waveform of the vertical deflection output circuit 2, and the voltage _E1 represents the threshold level of the negative pulse detection circuit 8 which should become a trigger pulse. B in the figure is the output waveform of the negative pulse detection circuit 8, and C in the figure is the output voltage of the vertical deflection output circuit 2.

During the scanning period, the vertical deflection drive circuit 1,
Since the vertical deflection output circuit 2 is operating normally, the input voltage of the vertical deflection output circuit 2 is a superposition of the bias voltage of the first stage element and the sawtooth voltage applied to the terminal 12. However, during the retrace period, the feedback loop consisting of the vertical deflection drive circuit 1, the vertical deflection output circuit 2, and the feedback circuit 4 is broken due to the retrace pulse generated in the vertical deflection coil 7. The first stage element is cut off, and a negative pulse is generated as shown in the _TR period of FIG. 5A. By using a comparator with a threshold level such as voltage _E1 in the negative pulse detection circuit, a positive pulse as shown in FIG. can.

FIG. 6 is a specific circuit diagram according to an embodiment of the present invention, in which a vertical deflection output circuit 2, a power supply pump-up circuit 3, and a negative pulse detection circuit 8 are formed in one integrated circuit. 5 is a capacitor, 6 is a diode, and 7 is a deflection yoke. Vertical deflection output circuit 2
are transistors Q ₁ to _{Q 4} , Q ₇ , Q ₉ , Q ₁₁ to _{Q 15} ,
Consists of diodes D ₁ , D ₂ , D ₄ , and D ₅ . In particular, transistor Q ₃ is the input stage, its base is a resistor
The emitter is connected to the input terminal through _R5 and is a resistor.
Connected to ground via _R8 . Current is supplied from transistor Q ₄ to resistor R ₈ to generate a voltage drop, biasing the emitter of Q ₄ . The power pump up circuit is a transistor
It consists of Q ₁₆ to Q ₂₈ , Q ₈ , and Q ₁₀ . In addition, diode D ₆
is a clamp diode like diode _D7 . Further, the transistors Q ₂₅ and Q ₂₇ are circuits that externally change the voltage charged to the capacitor 5 to make the vertical retrace period variable. The pump-up trigger pulse detection circuit 8 includes a transistor Q6 whose base is connected to the input terminal via a resistor _R6 and whose emitter is directly connected to the ground point, and a transistor _Q5 serving as a collector load of the transistor _Q6 . Therefore,
Transistor Q ₆ has a lower threshold level than transistor Q ₃ and is reliably in the on state during _the vertical scanning period. detects the pulse and controls the power pump up circuit 3.

In the first half of the vertical scanning period, transistors Q ₁₁ , Q ₁₄ ,
In the latter half, the deflection yoke 7 is driven by the transistors Q ₉ and Q ₁₅ . First stage transistor during scanning period
Since the base of Q ₃ has a superposition of the bias voltage and a vertical sawtooth voltage, transistor Q ₆ with an appropriate threshold level below that voltage is on, and the junction b ₂
does not exceed Vcc, so transistor _Q16 is off. Since transistor Q ₆ is on, transistors Q ₂₁ and Q ₂₀ are off, and transistor Q ₁₆
are off, so the transistors Q ₁₇ , Q ₁₉ , Q ₂₃ ,
Q ₂₄ is turned off, transistor Q ₁₈ is also turned off, and eventually transistors Q ₈ , Q ₁₀ and Q ₂₆ are turned off. On the other hand, transistor _Q28 is biased through resistor _R32 and turned on. connection point b ₁
Since is grounded, the capacitor 5 is charged to the power supply voltage.

During the retrace period, the feedback loop is broken by the retrace pulse generated by the deflection coil 7, so the first stage transistor _Q3 is turned off, and when its base potential falls below the threshold level of the transistor _Q6 , the transistor _Q6 is turned off. Therefore, a positive pulse is generated at the collector of transistor _Q6 .
This trigger pulse turns on transistor Q ₂₁ , causing current to flow through resistor R ₂₉ and turn on transistor Q 21.
Q ₂₀ turns on. As a result, transistor Q ₁₈
is turned on, and transistors Q ₈ , Q ₁₀ , and Q ₂₂ are turned on. Because transistor Q ₂₂ turns on
Q ₂₈ is off. On the other hand, the current in the deflection coil 7 during the first half of the retrace period flows through the diode D ₆ , the capacitor 5, and the diode D ₇ to the current V _CC .
At this time, the voltage at point _b2 exceeds the power supply voltage _Vcc , so transistor _Q16 is turned on. When Q ₁₆ is turned on, Q ₁₇ is turned on, and as a result, base current flows through Q ₂₃ , Q ₂₃ , Q ₂₄ , and Q ₂₆ are turned on. Thus,
The supply voltage to the vertical deflection output circuit 2 is the power supply voltage V _CC
It is almost twice as large as the previous year. Since transistors Q ₁₆ and Q ₁₇ are on while point b ₂ exceeds the power supply voltage V _CC , transistor Q ₂₆ remains on. Turning on _Q17 gives base current to _Q19 , so
Q ₁₉ is also on. Therefore, if the width of the trigger pulse is shorter than the retrace period, the transistor
Even if Q ₂₁ and Q ₂₀ are turned off, transistor Q ₁₉ remains
Give base current to Q ₁₈ , Q ₁₀ , and Q ₁₈ is Q ₁₈ ,
Since we give the base current to Q ₂₂ , the transistor
Q ₈ and Q ₁₀ are on, and Q ₂₈ is off. The current in the deflection coil 7 during the latter half of the retrace period is the transistor
Q ₂₆ , flows through capacitor 5 and transistor Q ₁₄ . Transistors Q ₈ and Q ₁₀ protect transistors Q ₉ and Q ₁₅ by cutting off transistors Q ₉ and Q ₁₅ during the vertical retrace period.

As described above, by adopting the configurations as shown in FIGS. 4 and 6, there is no need to create a pump-up trigger pulse with the vertical oscillator, and the degree of freedom in the configuration of the vertical oscillator increases. Further, since the vertical deflection output circuit IC to which the present invention is applied does not require an external pump-up trigger pulse, it can be used in most vertical deflection systems.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional pump-up type vertical deflection output circuit, Figures 2 A to D are voltage and current waveform diagrams of its main parts, and Figure 3 is a conventional vertical deflection output circuit corresponding to Figure 1. FIG. 4 is a block diagram of a vertical deflection output circuit according to an embodiment of the present invention, FIGS. 5A to 5C are voltage and current waveform diagrams of the main parts, and FIG. FIG. 2 is a circuit diagram showing a specific example of an embodiment of the invention. 1... Vertical deflection drive circuit, 2... Vertical deflection output circuit, 3... Power pump up circuit, 4...
Feedback circuit, 5... Capacitor, 6... Diode, 7... Deflection yoke, 50... Vertical oscillation circuit.

Claims (1)

[Claims] 1. An input terminal to which an input signal including a pulse indicating a vertical retrace period and a vertical deflection signal is supplied, and a vertical deflection coil connected to this input terminal and connected to a deflection output terminal in response to the vertical deflection signal. a vertical deflection output circuit to be driven; a first transistor connected between the pump-up output terminal and a reference potential point; a second transistor connected between the pump-up output terminal and a power supply potential point; and the pump-up output. By detecting the voltage of the deflection output terminal and a capacitor connected between the terminal and the power supply line of the vertical deflection output circuit, the first and second transistors are made conductive and non-conductive, respectively, during the vertical retrace period. Then, during the vertical scanning period, a power supply pump-up circuit having circuit means for rendering the first and second transistors non-conductive and conductive, respectively, a detecting means connected to the input terminal and detecting the pulse, and a signal from the detecting means are provided. and a trigger pulse control circuit having means for rendering the second transistor non-conductive in response to a detection signal, the vertical deflection output circuit having a base connected to the input terminal and an emitter connected to the reference through a resistor. a third transistor connected to a potential point, means for driving the vertical deflection coil in response to a collector output of the third transistor, and supplying a bias current to the resistor to drive the emitter of the third transistor. The detection means of the trigger pulse control circuit includes a fourth transistor having a base connected to the input terminal and an emitter directly connected to the reference potential point, and the fourth transistor A vertical deflection circuit characterized in that the detection signal is obtained from a collector of the vertical deflection circuit.