JPS5849921B2 - magnetic recording and reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic recording and reproducing apparatus for recording and reproducing additional information signals sent in a superimposed manner during the vertical retrace period of a television signal.

Conventionally, when recording a binary signal indicating additional information superimposed on the vertical retrace period of a television signal, a special VTR for broadcasting was used to directly record and play back the signal. If you try to record and play back this binary information signal using a home-use VTR, etc., it will be difficult to determine the shape of the sampling clock, and the waveform distortion will be large, making it difficult to shape the waveform. Ta.

Therefore, the present invention proposes a magnetic recording and reproducing apparatus that can be widely applied to recording and reproducing binary information signals transmitted using the vertical retrace period of television signals, such as the TELETEXT system.

An embodiment of the present invention will be described below based on the drawings.

First, as a home VTR used for recording and playback,
Consider the PAL standard.

As for the luminance component, it is only recorded in a frequency range lower than that of the carrier color signal.

Therefore, its recording limit is approximately 2 MHz.

In addition, as an information transmission system, the UK's TELETEXT
Taking a system as an example, a binary information signal of additional information is transmitted at the 17th H and 18th H during the vertical retrace period of a television signal, and the data rate at the time of transmission of the binary information signal is is 6. At 9 3 7 5 MHz, the highest frequency component of the fundamental wave is 3.4 6 8 7
It is 5MHz.

Therefore, the binary information signal transmitted superimposed on the television signal cannot be directly recorded on the VTR.

Therefore, the transmitted binary information signal is once written into a buffer memory and converted into a low-speed signal, that is, a low-frequency signal, before being recorded on the VTR.

For example, a signal transmitted during the IH period during the vertical retrace period of a television signal is written into a buffer memory, read out over a 2H period, converted to half the frequency, recorded on a VTR, and played back.

In some cases, the binary information signal thus converted to a lower frequency is phase-encoded and then recorded on a VTR and reproduced.

However, since the frequency doubles when performing phase encoding, the frequency should be converted to one-fourth or less beforehand.

In this embodiment, it is assumed that the binary sum signal is converted to a frequency of 1/2 as described above, and then recorded on a VTR and reproduced.

First, FIG. 1 shows a schematic block diagram of the entire apparatus of this embodiment, and FIG. 2 shows a waveform diagram.

The 17th H and the 1st H during the vertical retrace period of the television signal
At the 8th H, binary information as shown in FIG. 2A and B is superimposed and transmitted.

This signal is amplified by a buffer amplifier 2 in a receiving circuit 1 including a video detection circuit, and a first . 7 The two information signals of the I{th IH period are divided into 21{ periods and subjected to processing such as halving the frequency or phase encoding, and then added to the VTR 4 and amplified by the buffer amplifier 5. Recording is performed on a magnetic tape 7 using a recording head 6.

Here, as mentioned above, the binary information signal transmitted at the 17th I4 is divided into 2H periods and recorded at the 19th I{th and 20th H} in the form shown in Figure 2C. shall be taken as a thing.

The information signal 6 recorded on the magnetic tape 7 in this way is read out by the reproducing head 8, amplified by the buffer amplifier 9, and
At the 119th and 20th H, a reproduced signal as shown in FIG. 2C is obtained.

This is added to the signal reproducing circuit 10, where the waveform is shaped, and the sampling clock is regenerated using the clock line signal CR and the framing code signal FC, thereby sampling the reproduced signal. Obtain a binary signal.

First, n bits of the 19th H binary information signal are written into the buffer memory 11, and then n bits of the 20H binary information signal are written into the buffer memory 11.

After that, the 17th H (correctly the 33rd H) of the next field.
Following the control signal (CR signal and FC signal, total 24 bits), a 2n-bit binary information signal is read out from the buffer memory 8 in succession (0H), and the mixing circuit 12 reads the television signal reproduced from the VTR 4 at the 17H, i.e. It is superimposed on the original position and amplified by the buffer amplifier 13.

In this way, the television signal on which the reproduced information signal is superimposed is
Either output the video signal directly or output it with the RF conversion circuit 14.
The signal is converted to an F signal and output as a UHF signal or VHF signal.

By inputting this output signal to the video input terminal of the TELETEXT receiver or to the RF antenna input terminal, the TELETEXT signal in the broadcast television signal can be input.
The TELETEXT signal can be received from the reproduced signal of the VTR 4 in the same way as the EXT signal.

Additional information programs for supplementary explanations on the television screen can be displayed or erased using the TELETEXT receiver depending on the playback from the VTR4. The scope of application can be wider than when recording only the emotional axis alone.

FIG. 3 shows an example of the structure of the signal processing circuit 3, where 15 is a slice circuit which shapes the waveform of the output of the buffer amplifier 2 into a binary signal.

16 is a synchronous separator 17 is a clock recovery circuit, as shown in Fig. 2H.
A sampling clock is recovered from the CR signal among the binary information signals output from the slice circuit 15 shown in FIG.

18 is a gate pulse generation circuit that generates a gate pulse that becomes high level at the 171.1st from the vertical and horizontal synchronization signals output from the sync separation circuit 16; 19 and 20 similarly generate gate pulses at the 19th and 20th H. This is a gate pulse generation circuit that generates gate pulses each having a high level.

21 is a gate circuit which extracts the binary information signal of TELETEXT which is actually folded at the 17th H.

According to the TELETEXT system standard, a signal is also superimposed on the 18th H, but it is omitted here to simplify the explanation.

It is sufficient that the 18th H signal is subjected to the same processing as the 17th H signal.

22 is a buffer memory for IH, and if a total of 2n bits of information signal is superimposed on the 17th H as shown in Fig. 2A, the buffer memory 22 needs to have a storage capacity of 2n bits or more. .

23 is a control circuit for writing and reading from the buffer memory 22; 24 is the 17th IH from the buffer memory 22;
This is a code generation circuit for inserting a sequence code in front of the signals when half of the information @ is read out at the 19th H and 20th H.

At the 19th H, the control circuit 23 reads out the n-bit binary information signal in the first half of the 20-bit signal stored in the 8th sofa memory 22, and the code generation circuit 24 reads the 20-bit signal stored in the 8th sofa memory 22 as shown in FIG. Add an order code as shown in D1,
As shown in FIG. 2C, the signal is supplied to the N/T mixing circuit 25, mixed with the input television signal, and added to the VTR 4 for recording.

VTR4 is a home VTR (for example, % inch type)
is sufficient.

Next, in the 20th H, the remaining n bits are read out from the buffer memory 22 in the same manner as shown in FIG.
5 and recorded on the VTR 4.

The order code at this time is D2 in FIG.

Here, the redundant television signals (video detection signals) of the 19th and 20th H during horizontal scanning are removed.

Note that if the divided recording is correct and is performed at the 19th and 20th H, it is not necessary to use this order code, but
If synchronization switching of broadcasting stations is taken into account, the operation is more reliable when sequential codes are used.

In this way, the 17th H binary information signal is divided into the 19th H and 20th H, and the frequency is reduced to 1/2, and the VTR 4
can be recorded.

Note that the 20-bit information signal includes various control signals in addition to code signals representing characters and figures.

Next, the operation of this part will be described in more detail with reference to Figures 4 to 6.

First, in FIG. 4, the second
A pulse is generated to extract the CR signal portion of the binary information signal shown in FIG.

That is, a horizontal synchronizing signal triggers two continuously connected monostable multi-stages to form a partial input signal of the CR signal.

This pulse operates the resonance circuit 27 to extract only the CR signal and cause it to resonate, and the ringing generation circuit 28 (including a crystal resonator) generates a ringing signal that lasts for about 1H period or more, and the waveform shaping circuit 29 shapes the waveform. to set the sampling clock.

More detailed information on these matters can be found in the patent application filed in 1973 by the applicant.
It is described in No. 228840.

This sampling clock output is taken out by the AND gate 30 only at the 17th H, and is supplied to the framing code FC detection circuit 31 to detect the FC signal and clear the address counter 32.

Thereafter, the address counter 32 counts the sampling clock applied via the OR gate 33 and specifies the address of the buffer memory 22.

On the other hand, the buffer memory 22 is in a write mode during the 17th H when the output of the gate pulse generation circuit 18 is at a high level, and is in a read mode when it becomes a low level.

Therefore, 2n bits of information are written into buffer memory 22.

The number of output pulses of the sampling clock generation circuit 17 is F
If the address counter 32t is set to 20 bits after the C signal is detected, and the address counter 32t is set as a 2n-bit counter, the address returns to the original state again after clocking the address counter 32 by 2n bits.

In this manner, after writing a 2n-bit information signal to the expander memory 20 at the 17th H, the read clock of the output of the gated oscillation circuit 34 is supplied to the address counter 32 at the 19th H.

Therefore, the contents of the buffer memory 22 are read out by the read clock applied from the gated oscillator 34 at the 19th H.

This gated oscillation circuit 34 generates a read clock having a frequency that is one-half that of the above-mentioned sampling clock.

On the other hand, the code generation circuit 24 includes two sets of ROMs 35 and 36 and their address counters 37 for generating the CR signal, FC signal, and order signal among the recording signals shown in FIG. 2C. .

ROM35 is set with a CR signal, FC signal, and a sequence signal such as D1, and ROM36 is set with a CR signal and FC signal.
A signal and an order signal such as D2 are set.

At the 19th H, a pulse from the gate pulse generating circuit 19 puts the ROM 35 into an operating state, and at the 20th H, a pulse from the gate pulse generating circuit 20 puts the ROM 36 into an operating state.

As described above, prior to reading n-bit information signals from the buffer memory 22, a 32-bit read clock for reading the CR signal, FC signal, and sequence signal from the ROM 35 or ROM 36 is supplied to the address counter 37.

The signals read from ROM35 and 36 are sent to AND gate 3.
8 to the OR gate 39 as well as the buffer memory 22
The signal is combined with the information signal read out through the AND gate 40.

AND gates 38 and 40 are controlled by gate pulses from gated oscillation circuit 34, making AND gate 38 conductive only during readout periods of the CR signal, FC signal, and sequential signal, and AND gate 40 being conductive during other periods.

At the 19th H, the CR signal from ROM35, the FC
After reading out the signal and the order signal D1, the n-bit read clock is output from the gated oscillation circuit 34 to the OR gate 3.
3 to the address counter 32 and reads out the first half of the information signal from the buffer memory 22 up to the n-th bit,
These are combined and recorded on the VTR 4 in the form shown in Figure 2C.

At the 20th H, after reading the CR signal, FC signal and order signal D2 from the ROM 36, the buffer memory 22
The latter n bits of the information signal are read out from the data signal, and they are combined and recorded on the VTR in the form shown in FIG. 2C.

In this way, the received 17th H binary information signal is converted to 1/2 the frequency, and the 19th H of the television signal is converted to 1/2 the frequency.
It is possible to record on the VTR 4 by superimposing half of each on the H-th and 20th H-th.

The binary information signal sent at the 18th H may also be processed in the same manner by a similar circuit, and half of it may be superimposed on the 21st H and 22nd H and recorded on the VTR 4.

Next, the portion of the signal reproducing circuit 10 that processes the signal reproduced from the VTR 4 and shapes the waveform will be explained.

This part mainly consists of a sampling circuit and a slicing circuit, and its outline is shown in FIG.

Here, the reproduced signal from the VTR 4 is transmitted to the emitter follower 4.
1, the pedestal level is clamped by a clamp circuit 42, and then a binary signal is reproduced by a slice circuit 43 and applied to a sampling circuit 44.

On the other hand, the CR signal in the reproduced signal is extracted by the gate circuit 45 and the fundamental frequency of the clock (6.9 3 7 5 MH
only one half of z) is amplified by the band amplification circuit 46.

Next, the CR signal is differentiated by a doubling circuit 47 to obtain 2
After being multiplied by a 6.9 3 7 5 X-MHz band amplification circuit 48, a continuous wave that continues at least during the horizontal period is obtained by adding it to a resonant circuit having a crystal resonator, and this is amplified by a waveform shaping circuit 50. and slice to obtain TTL level sampling relock.

Using this signal, the sampling circuit 44 samples the signal and reproduces the binary information signal.

On the other hand, 51 is a detection circuit that detects the FC signal from its output, and when it detects the FC signal, it controls the clock generation circuit 52 and sends an 8-bit sequential signal as shown in FIG. The first half of the signal is identified by supplying a clock for extracting the address counter 5.
4 and supplies the address counter 54 with an address generation clock for writing n bits of information signal into the buffer memory 11.

Next, in this way, from the VTR 4, the 19th and 20th
The portion where the information signal reproduced over the 2H period of the H-th signal is converted to a high frequency again and is superimposed on the 17th-H television signal will be described in detail with reference to FIG.

As mentioned above, in order to combine the binary information signals recorded and reproduced in the 2H period of the 19th and 20th H into the IH period, it is necessary to determine whether the reproduced signal is from the first half or the second half. It is necessary to judge.

This determination is made by detecting the sequence signals included in the 19th and 20th H information signals being reproduced and output from the VTR 4. The detection circuit 55 detects the sequence signal D1 and the detection circuit 56 detects the sequence signal D2.

That is, first, the sampling circuit 4 as shown in FIG.
The output from 4 is added to the shift register 57, written with a sampling pulse as shown in FIG.

According to the FC signal detection output, that is, Fig. 7C, the 19H
At the beginning of the eye and the i20H eye, there is a fluff 0 fluff 59
Set as shown in Figure 7D.

When the Q output D becomes high level, the detection circuit 55. 56
When the sequence signals D1 and D2 are detected as shown in E, a detection output is generated.

When the order signal for the first half is detected and reaches 7, the address counter 54 is reset to specify the address of the first half of the buffer memory January 1, and the address is changed by the clock F with a slight delay time. memory 1
The n bits of the reproduction information signal of the first half are written in the first half of 1.

At this time, since the gate pulse generating circuit 6o does not generate a gate pulse except for the 17th H, the AND gate 61 becomes conductive and the sampling clock is transferred to the address counter 54.
supply to.

Therefore, the address of buffer memory 11 changes in synchronization with the sampling clock.

When the second half order signal D2 is detected at the 20th H, the address counter 54 is similarly preset to designate the second half address of the buffer memory 11, and n bits of the second half reproduction information signal are written in the second half of the buffer memory 11.

In this way, the 20 bits of the reproduction information signal of the first half and the second half can be successively written into the buffer memory 11.

Therefore, this information signal is read out at the 17th H of the next field.

That is, in the 17th H, the gate pulse generation circuit 60 composed of a counter, FF, etc. counts a predetermined number of read clocks and generates a gate pulse for the control 1 signal period and a nokate pulse for the information signal period.

With this gate pulse, the control signal period becomes AND gate 6
3 becomes conductive and reads out the 24-bit control signal generated by the control signal generation circuit 62C, that is, the CR signal and the FC signal.

Three 8-bit shift registers or ROMs may be used as the control signal generation circuit 62C.

When a gate pulse for the information signal period is generated, the AND gate 63 becomes conductive, applies a read clock to the address counter 54, and continuously reads 2n bits of information signals from the buffer memory 11.

Moreover, since the AND gate 64 is also conductive at this time, D-
The information signal read from the buffer memory 11 is input to the flip-flop 65.

This I}-FF 65 samples a binary information signal.

The original binary information signal as shown in FIG. 2B can be obtained from this D-FF 65 at the 17th H.

In the above manner, the VTR4 is
or read the information signal from the 17th H of the next field.
It can be output to the eyes.

The above explanation was about recording and reproducing the binary information signal superimposed on the 17th H of the television signal, but in the TELETEXT system, the binary information signal is also superimposed on the 18th H, and this is transmitted to the VTR4. ? The point that the data is recorded in the 21st H and the 22nd H, read out, and reproduced is the same as described above.

However, in this case, writing to the buffer memory 11 requires some consideration, so this point will be described in detail with reference to FIG. 8.

First, during writing, when the detection circuit 55 detects the first half order signal D1 at the 19th H, the FF 66 is set,
Set its Q output to high level.

Since this FF 66 is reset with a vertical pulse and then applies the detection output from the FC detection circuit 51 (FIG. 5) to the J terminal, it changes from a low level to a high level when the order signal D1 is detected.

The detection circuit 67 detects this change and resets the address counter 54 via the OR gate 68.

Therefore, in the 19th H, Banfa memory lJ11A, 11
At this time, the first half address of each of B is specified.
Since the output of OR gate 69 is at a high level due to the Q output of F66, AND gates 70 and 71 become conductive and apply the sampling clock to address counter 54, changing the addresses of buffer memories 11A and 11B in synchronization with this. .

The two sets of buffer memories 11A and 11B are controlled by the output of the OR gate 72. During the 19th, 20th, and 17th H, the buffer memory 11A is activated, and during the other periods, the buffer memory IJ11B is activated. do.

Therefore, the 19th H information signal is in the buffer memory 11A.
will be written in.

On the other hand, in the 20th H, since the output of the AND game 173 has reached a high level by then, when the detection circuit 56 detects the second half order signal D2, the E 74 is set.

As a result, the output of the OR gate 69 becomes high level,
A sampling clock is added to the address counter 54 in the same way as the 19th H above.

However, at this time, the address counter 54 specifies the address in the latter half of the buffer memory 11A, and the 20Hth information signal n bits are written in the latter half of the buffer memory IJ11A.

Even in the 17th H of the next field, the buffer memory lJ11
Since A is in the operating state and the output of the OR gate 73 is at a high level, the AND gate 71 is cut off and the AND gate 7
4 becomes conductive.

Therefore, in this case, 6. A read clock of 9 3 7 5 MHz is applied to the address counter 54 to designate an address and read out the information signal.

On the other hand, due to the gate pulse output from the gate pulse generating circuit 60 during the information signal period, the buffer memories 1J11A and 11B enter the read state after the FC signal, and the AND gate 74 also becomes conductive, as described above.
A 2n-bit binary information signal is read from 1A and 11B.

However, at the 17th H, the AND gate 75 becomes conductive and outputs the binary information signal from the buffer memory IJ 1 1 A.

Next, in the 21st H and 22nd H, the output of the OR gate 72 is at a low level, so the buffer memo IJ1
1B becomes active and an information signal is written to it.

Other operations are the same as in the 19th and 20th H cases described above.

The 21st and 22nd H information signals are stored in the buffer memory 1.
At the 18th H of the next field written in 1B, the AND gate 76 becomes conductive and outputs a binary information signal from the buffer memory 11B.

As described above, the information signals read from the VTR4 at the 19th and 20th H are stored in the buffer memory lJ11A i21.
The information signals read out at the H-th and 22nd H-th are written from the write memory IIA to the 17th H-th (
From the buffer memory 11B, the first field of the next field is
Since it is read out at the 8th H, the TELETEXT information signal transmitted through television broadcasting can be recorded on the VTR 4, reproduced, and output in the same form as the original television signal.

Therefore, the TELETEXT receiver can be operated with this output signal.

Although the above example is for the TELETEXT system, it goes without saying that binary information signals of other systems can be handled in the same way.

Further, if the information signal is superimposed only on the IH period, the circuit becomes simpler.

Furthermore, the same applies to pattern transmission.

As detailed above, according to the present invention, the binary information signal of the additional information koji transmitted superimposed on the television signal is converted to a lower frequency and then superimposed on the television signal again. It is possible to record on a simple device such as a VTR, and to convert the binary information signal reproduced from the VTR, etc. back to its original high frequency and superimpose it on the original position of the television signal. This makes it possible to obtain a convenient device that can directly input and receive the reproduced signal into an information receiver.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram of a magnetic recording/reproducing apparatus according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part thereof, FIGS. 3, 4, 5, 6 and 8 are detailed block diagrams of the main parts, and FIG. 7 is a waveform diagram of each part. 1... Receiving circuit, 2... Buffer amplifier 3... Signal processing circuit, 4... VT
R, 7...Song magnetic tape, 10...Signal reproducing circuit 11...Song buffer memory, 12...Mixing circuit.

Claims (1)

[Claims] 1. Extract the binary information signal of additional information superimposed and transmitted during the vertical retrace period of the television signal and write it to the buffer memory. Convert the above binary information signal to a lower frequency and read it from this buffer memory, and read the above mentioned binary information signal. The binary information signal is recorded on a magnetic recording medium by being superimposed on the vertical retrace period of the television signal, and the binary information signal reproduced from this magnetic recording medium is written into a buffer memory, and the buffer memory converts it to a high frequency of Ramoto and reads it out. 1. A magnetic recording/reproducing device characterized in that the magnetic recording/reproducing device is configured to output data in a superimposed manner.