JPS584936A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS584936A
JPS584936A JP10298581A JP10298581A JPS584936A JP S584936 A JPS584936 A JP S584936A JP 10298581 A JP10298581 A JP 10298581A JP 10298581 A JP10298581 A JP 10298581A JP S584936 A JPS584936 A JP S584936A
Authority
JP
Japan
Prior art keywords
substrate
adhesive
holes
active matrix
flat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10298581A
Other languages
Japanese (ja)
Inventor
Yasuo Katsuyama
勝山 恭雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP10298581A priority Critical patent/JPS584936A/en
Publication of JPS584936A publication Critical patent/JPS584936A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To provide a warpage free substrate by a method wherein a very flat glass substrate is provided with a predetermined number of holes, a fine glass fiber containing adhesive agent is applied thereto following a desired pattern, an Si substrate is vacuum adsorbed thereto with the help of the holes, and an active matrix substrate is mounted on the Si substrate after the setting of the adhesive agent. CONSTITUTION:A flat glass substrate 501 substantially thicker than an Si substrate 504 is provided with holes 503 and the surface of the substrate 501 is prescribedly coated after a prescribed pattern with adhesive 502 except the place where the holes are located. The adhesive 502 can be of either organic or inorganic substance and contains fine glass fiber with its diameter from several ten to several hundred micrometers. The holes are used to adsorb the substrate 504 whose surface is then irradiated by ultraviolet rays or heat rays for the setting of the adhesive 502. This results in a warpage free substrate whereupon an active matrix substrate is mounted securely upon the location of adhesive application.

Description

【発明の詳細な説明】 本発明#:r極めて平担な基板に半導体集積回路を一定
することに関する。WKは該半導体集積回路を平担化す
る方法及び該基板の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the mounting of semiconductor integrated circuits on extremely flat substrates. WK relates to a method for planarizing the semiconductor integrated circuit and a structure of the substrate.

シリコン基&表面にMO13スイッチングトランジスタ
及び電荷保持用コンデンサを形成して放るアクティブマ
トリクス基11HLVc工9構匠される大容量液晶ディ
スプレイでij、該了クチイブマトリクス基板と、上部
電極でthゐガラス板との間を液晶層とする為に、数ミ
クロンメートルの一様のギャップを保つことが必要であ
る。
It is a large-capacity liquid crystal display designed with an active matrix base 11HLVc engineered by forming MO13 switching transistors and charge retention capacitors on the silicon base and surface, and the active matrix substrate and the upper electrode are made of glass. In order to form a liquid crystal layer between the plate and the plate, it is necessary to maintain a uniform gap of several micrometers.

従来のアクティブマトリクス基板上に液晶を注入するア
センブル工程の断WJ図を第1図に示す。
FIG. 1 shows a cross-sectional WJ diagram of an assembling process for injecting liquid crystal onto a conventional active matrix substrate.

図中101はアクティブマトリタス基板でToO110
2はガラス板であり、103はシール材であると共にア
クティブマトリタス基鈑とガラス板とのギャップをコン
トロールする為のスペーサであり、104iltシール
材に工り一様なギヤツブ管有する液晶層であり、液晶注
入穴105から液晶層に液晶を注入する。現在液晶層の
ギャップ#18〜lOミクロンメートルと極めて薄く1
g晶表示ディスプレイの表示性能の重1!なファクター
である。
In the figure, 101 is an active matrices substrate and ToO110
2 is a glass plate, 103 is a sealing material and a spacer for controlling the gap between the active matrix substrate and the glass plate, and 104 is a liquid crystal layer having a uniformly machined gear tube in the sealing material. , liquid crystal is injected into the liquid crystal layer from the liquid crystal injection hole 105. Currently, the gap in the liquid crystal layer is extremely thin at #18 to 10 micrometers.
The importance of the display performance of the g-crystal display! This is a significant factor.

前記ギャップを一様に液晶表示面積内て保つ1ハ第1と
して上部ガラス板が平らであること、第2としてアクテ
ィブマトリクス基板が平らであること等が必要である。
In order to maintain the gap uniformly within the liquid crystal display area, it is first necessary that the upper glass plate be flat, and secondly that the active matrix substrate be flat.

*配属1の問題は、フラットガラス板のように!1面の
凸凹が数ミクロンメートル以下の基準を充分満足するも
のが市販されて1為ので容易に解決できる。
*Assignment 1's problem is like a flat glass plate! This problem can be easily solved because there is one on the market that fully satisfies the standard of not more than a few micrometers of unevenness on one surface.

II意の問題ではシリコン基板の表面は、理想的には全
く平らであることが望ましいが実際に#1基板製作時、
あゐいはプロセス−0間に変形すゐことがあり、1!@
に納入されたシリコン基板を平面1測定器により、数W
枚測定した結果、@2図に示されゐ1うなソリ返〕を有
していた。@2図は代表的なソリ返りを示しており、田
は上に凸であり。
Regarding the second problem, it is ideal that the surface of the silicon substrate is completely flat, but when actually manufacturing the #1 substrate,
Ai may be transformed between process and 0, and 1! @
A silicon substrate delivered to
As a result of measuring the sheet, it was found that it had the same warpage as shown in Figure 2. Figure @2 shows a typical warping pattern, with the field convex upwards.

mは下に凸であ、a、rFIは前記山及び(ト)のソリ
返1形状の両方を有しているものであゐ、ソリ返p量S
は数さクロンメートルから数10ミクロンメート〜とば
らつきが大きく%50嘔位は10きクロンメートル以上
のソリ返りを有していた・ 更に複雑に、[径方向I/c、凸になる方向と凹和なる
方向が直交する1うな形状(鞍II)を有するもの41
11I定された。次にプレセスの関KtIa生する変形
を示す1例えばシリコン基板を蔦温で熱酸化すると1表
面Krl化膜(8(Osl[)が形底される。
m is downwardly convex, a and rFI have both the above-mentioned mountain and (g) warp return 1 shape, and warp return p amount S
The variation was large, ranging from a few micrometers to several tens of micrometers, and the warpage at the %50 position was more than 10 micrometers. 41 having a one-sided shape (saddle II) in which the concave and sum directions are orthogonal
11I was established. Next, for example, when a silicon substrate is thermally oxidized at a heat temperature, a Krl film (8 (Osl[)) is formed on the surface of the silicon substrate.

該シリコン基板を室I!まで冷却すれば、シリコンと酸
化I[は熱膨張係数の違いに工す、内部応力と曲げモー
メンシを生じながち収縮すす、更に裏面の酸化膜を除去
するとシリコン基板は第3図に示すように湾曲すす、シ
リコン基板301tj酸化膜302に比べ熱膨張係数が
約−桁大きいので湾曲の方向は酸化膜儒凸和なる。tt
&tllL2の例としてFs、プロセスに於いてFi、
酸化膜の形醒や不純物の拡散の為に、 a!;温の熱感
IIが繰p返し行なわれてhる。この際に1鋏基板が一
様な温gK保たれたまま加熱、冷却されないと、該基[
[は熱応力が尭生する。この応力が充分に大きいとシリ
ーン基板#′i朧性変形を起こし、プロセスの終了後K
Place the silicon substrate in chamber I! If the oxide film on the back side is removed, the silicon substrate will shrink as shown in Figure 3. Since the curved soot has a coefficient of thermal expansion about an order of magnitude larger than that of the silicon substrate 301tj oxide film 302, the direction of the curve is the sum of the oxide film and the convexity. tt
As an example of &tllL2, Fs, Fi in the process,
Due to the deformation of the oxide film and the diffusion of impurities, a! ; Warm heat sensation II is repeated p and h. At this time, if one scissor substrate is not heated and cooled while maintaining a uniform temperature gK, the group [
[Thermal stress increases. If this stress is large enough, it will cause a hazy deformation of the silicon substrate #'i, and after the process is finished, K
.

基板のソリ返やとして観察される0以上のLうにプロセ
スに於けるソリ返りの弗化原因ij、大まかKはシリコ
ン基板と、骸基板の上に形面された他の物質との熱膨張
係数の差にもとず〈変形と、熱応力に起因すゐ変形の二
種類あ為、プロセスを全て終了し完医したアクティブマ
トリクス基板Kll。
0 or more L observed as substrate warpage The cause of warpage fluorination in the sea urchin process ij, roughly K is the thermal expansion coefficient between the silicon substrate and other materials shaped on the skeleton substrate Based on the difference between the two types of deformation and deformation caused by thermal stress, the active matrix substrate Kll has undergone all processes and is completely cured.

轟然ソリ返りが発生し、アセンプル工程での歩留りの低
下の原因となる。艷には、ソリ返りを数ミクロンメーシ
ル位に抑えることが困難であり、前記ギャップのばらつ
きが多くなp2表示性能の低下の原因となる。
A sudden warping occurs, which causes a decrease in yield in the assembly process. It is difficult to suppress the warping of the bar to a few micrometers, and the variation in the gap causes a decrease in the p2 display performance.

本発明はかかる欠点を除去した亀ので、その目的は、ア
クティブマトリクス基板のソ1J返pを。
The present invention eliminates such drawbacks, and therefore its purpose is to improve the reliability of active matrix substrates.

極めて平担な基板をパックプレーhとすることによ0矯
正すゐ方法と骸基板の構造を提供することであ為。
This is achieved by providing a method for zero correction by making an extremely flat board into a pack play h, and a structure of a skeleton board.

11!4恥、第S図及び諺6図に工す本妬明の冥施例を
詳細に説明する0図面の簡単な説明を次に示す、401
.501.@OXは、フラットガラス基板であり、シリ
コン基1fi#!c比べて充分厚さがある。
11! A brief explanation of the 0 drawing that explains in detail the example of the envy that is applied to 4 Shame, S Figure and Proverb 6 Figure is as follows, 401
.. 501. @OX is a flat glass substrate with silicon base 1fi#! It is sufficiently thick compared to c.

402.502,603!は無機又!fi有機系の接着
材に直径が例見は数十ミクロンメートル−百数十iタロ
ンメートル(必ずしもそれに限ゐものではなη)の一様
の直径を有するグラスファイバーを混合した物で、#接
着材は紫外線又は熱線の照射又はそれ以外条件で硬化す
るものである。403.503.6031j該ガラス基
板の穴である。504.604はアクティブマトリクス
基板である。
402.502,603! is inorganic! fi is a mixture of organic adhesive and glass fiber having a uniform diameter, for example, tens of micrometers to hundreds of talons (not necessarily limited to η); The material is cured by irradiation with ultraviolet rays or heat rays or other conditions. 403.503.6031j A hole in the glass substrate. 504 and 604 are active matrix substrates.

605は樹脂である。#フラツ奈ガラス基板表面tit
理想的な平面(凸凹が数2クロンメートル以内)を有す
るものであり菖4g1に示すように、接着材402を骸
ガラス基板褒面に印刷、する、該接着材の印刷パターン
は一番外局が閉じておI、それ以外のパターンは少なく
と41個所以上が開いており、穴を塞がなければよ<、
 IN4図は一例である。該穴は骸印刷バターyの内@
にあり、少なくとも1個以上は設けA*j15a#15
g4図の断面−であり1wc着材の上にアクティブマト
リクス基板504を乗ぜる。それから穴に真空ポツプを
接続し、該アクティブマトリクス基板を真空散着すムと
、大気圧に1つて骸基板は、接着材中のグラスファイバ
ーをストッパーとして−wKrIk着スる。
605 is resin. # Flat glass substrate surface tit
The adhesive material 402 is printed on the surface of the skeleton glass substrate, as shown in iris 4g1, which has an ideal flat surface (the unevenness is within a few metric meters).The printing pattern of the adhesive material is Close it, but the other patterns have at least 41 holes open, so you have to close them.
The IN4 diagram is an example. The hole is inside the Mukuro printing butter y@
and at least one or more A*j15a#15
The active matrix substrate 504 is placed on top of the 1wc adhesive material, which is the cross section of Figure g4. Then, when a vacuum pot is connected to the hole and the active matrix substrate is vacuum-sealed, the shell substrate is attached to -wKrIk using the glass fiber in the adhesive as a stopper at atmospheric pressure.

且つ接着材は前記の性質を有し、使用接着材に遍し大条
件で硬化する。更#C該接着材が硬化彼、第6■に示す
工うに、アクティブマトリクス基板と。
Moreover, the adhesive has the above-mentioned properties and cures under a wide range of conditions regardless of the adhesive used. After the adhesive is cured, the process shown in Section 6 is performed with an active matrix substrate.

平担な基板とのスペースを前記穴から樹脂を注入して充
填すゐ。
Fill the space between the flat board and the board by injecting resin through the hole.

本発Wj4により、アクティブマトリクスai−板は。With this Wj4, the active matrix AI-board is.

バッタプレーがであるガラス基板表面の理想的な平面形
状にグラスファイバーを介して平面矯正され、更に樹脂
を注入し完全に固定される為に、該アタテイプマトリク
ス基板がプロセス終了*、カなりソリ返りが斃生し責と
しても、平面矯正することができる。し霞がりて8〜1
0 iクロンメートルのギャップを一様に保つことがで
き1表示性能の大幅な改豐ができることは明らかである
The grasshopper plate is flattened to the ideal planar shape of the glass substrate surface through the glass fiber, and then resin is injected to completely fix it, so that the attape matrix substrate is completely fixed at the end of the process*. Even if the curve is caused by deformation, the plane can be corrected. It's hazy 8-1
It is clear that it is possible to maintain a uniform gap of 0 i chrome meters and to significantly improve the display performance.

本賽施例では、liめて平担な基板としてガラス′iI
&eを適用したがそれに@ゐものではなく、該ガラス基
板と同等あるいけそれ以上、平担な基板であれば艮い。
In this example, glass 'iI was used as a flat substrate.
&e was applied, but it is not @ゐ, and it is fine if it is a flat substrate that is equal to or even more flat than the glass substrate.

aa面の簡単*i52#l 第111けアクティブマドvクス基板のアセンプル工程
の断面図である。
It is a sectional view of the simple *i52#l 111th active mask V-customer board assembly process on the aa plane.

8267Aはシリコン基板の納入W#に測定し大、ソリ
返pの代豪的な形状であゐ。
8267A has a large shape as measured by the delivered silicon substrate W# and a large warpage P.

合の湾曲形状である。It has a curved shape.

第4図は本尭明の実施例の概観−である。FIG. 4 is an overview of Takaaki Moto's embodiment.

鮪5図、第6図は本鞄明の実施例の断面■である。Figures 5 and 6 are cross-sectional views of the embodiment of this bag.

以   上 出1人 株式会社諏訪精工舎 代理人 弁理士最 上  務 第1図 第2目 第3図 第4図that's all 1 person: Suwa Seikosha Co., Ltd. Agent Patent Attorney Mogami Figure 1 Second eye Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] (1)  極めて平担な基板上に、少なくとも1個以上
の穴を開FT、該基板表面にグラスファイバーを混合し
た接着材を適当なパターンで印刷し、該パターン上に半
導体集積回路を乗せた後、該穴を介して真空吸着を行な
い、且つ前記接着材を硬化させて放ることを特徴とする
半導体集積回路。 1z  半導体集#lrgl路と平担な基板とのスペー
スを。 前記穴から樹脂を注入して充填することを特徴とする特
軒藷求の範囲第一項記載の半導体集積回路。
(1) At least one hole was made on an extremely flat substrate, an adhesive material mixed with glass fiber was printed on the surface of the substrate in an appropriate pattern, and a semiconductor integrated circuit was placed on the pattern. After that, vacuum suction is performed through the hole, and the adhesive is cured and released. 1z Semiconductor collection #lrgl space between the path and the flat board. The semiconductor integrated circuit according to item 1 of the scope of claim 1, characterized in that resin is injected and filled through the hole.
JP10298581A 1981-06-30 1981-06-30 Semiconductor integrated circuit Pending JPS584936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10298581A JPS584936A (en) 1981-06-30 1981-06-30 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10298581A JPS584936A (en) 1981-06-30 1981-06-30 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS584936A true JPS584936A (en) 1983-01-12

Family

ID=14342002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10298581A Pending JPS584936A (en) 1981-06-30 1981-06-30 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS584936A (en)

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