JPS5849275U - test adapter - Google Patents

test adapter

Info

Publication number
JPS5849275U
JPS5849275U JP14532781U JP14532781U JPS5849275U JP S5849275 U JPS5849275 U JP S5849275U JP 14532781 U JP14532781 U JP 14532781U JP 14532781 U JP14532781 U JP 14532781U JP S5849275 U JPS5849275 U JP S5849275U
Authority
JP
Japan
Prior art keywords
terminal
connector
test adapter
input
adapter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14532781U
Other languages
Japanese (ja)
Inventor
熊井　克至
信一 山田
国安　賢二
清宮　守
園部　健二
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP14532781U priority Critical patent/JPS5849275U/en
Publication of JPS5849275U publication Critical patent/JPS5849275U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例の斜視図、第２図は本考案め
一実施例の回路図である。 図中、ＴＡはテストアダプタ、ｓｗｇ〜５ｗ１５はスイ
ッチ、ＣＮＡ〜ＣＮＤはコネクタ、ＣＮ、　ＣＨ２はコ
ネクタ、ＰＣはプラグコードである。FIG. 1 is a perspective view of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an embodiment of the present invention. In the figure, TA is a test adapter, swg to 5w15 are switches, CNA to CND are connectors, CN and CH2 are connectors, and PC is a plug cord.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アナログ信号が入力される複数の入力端子を有する処理
装置と、アナログ信号を発生する発生袋、置とを有し、
該アナログ信号が入力されて該アナログ信号のレベルに
応じたデータを取扱う処理装置のテストアダプタであっ
て、該複数入力端子に着脱自在なコネクタと、該コネク
タの各端子に信号を供給する信号供給手段と、該コネク
タの各端子を選択する様、各端子と信号供給手段との間
に接続、切断自在に配置される複数のスイッチとを備え
て成るテストアダプタ。It has a processing device having a plurality of input terminals into which analog signals are input, and a generating bag and a place that generate analog signals,
A test adapter for a processing device to which the analog signal is input and handles data according to the level of the analog signal, the adapter comprising a connector detachably connected to the plurality of input terminals, and a signal supply supplying signals to each terminal of the connector. A test adapter comprising: means for selecting each terminal of the connector; and a plurality of switches arranged so as to be connectable and disconnectable between each terminal and the signal supply means so as to select each terminal of the connector.
JP14532781U 1981-09-30 1981-09-30 test adapter Pending JPS5849275U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14532781U JPS5849275U (en) 1981-09-30 1981-09-30 test adapter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14532781U JPS5849275U (en) 1981-09-30 1981-09-30 test adapter

Publications (1)

Publication Number Publication Date
JPS5849275U true JPS5849275U (en) 1983-04-02

Family

ID=29938261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14532781U Pending JPS5849275U (en) 1981-09-30 1981-09-30 test adapter

Country Status (1)

Country Link
JP (1) JPS5849275U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62172769U (en) * 1986-04-02 1987-11-02
JPS62172768U (en) * 1986-04-01 1987-11-02
JPS63112576U (en) * 1987-01-14 1988-07-20

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62172768U (en) * 1986-04-01 1987-11-02
JPS62172769U (en) * 1986-04-02 1987-11-02
JPH0316944Y2 (en) * 1986-04-02 1991-04-10
JPS63112576U (en) * 1987-01-14 1988-07-20
JPH0452298Y2 (en) * 1987-01-14 1992-12-09

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