JPS5848961A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a transistor, couple capacitance between a gate electrode and a drain region thereof is small, by forming at least the drain region in offset structure to the gate electrode and geometrically making a source region and the drain region asymmetrical to the gate electrode. CONSTITUTION:The gate electrode 402, which uses a gate oxide film 401 as an underlay and consists of polycrystal Si, is shaped onto a P type Si substrate 400, As ions 403 are implanted at an angle theta to a vertical surface, and the N type drain region 404 in offset structure to the electrode 402 is formed through heat treatment at a high temperature. The N type source region 405 geometrically asymmetrical to the region 404 is shaped into a region holding the electrode 402 at the same time. Accordingly, the couple capacitance between the gate electrode 402 and the drain region 404 is reduced without lowering the capability of the transistor.

Description

[Detailed description of the invention] The present invention relates to a semiconductor device.

Recently, there has been a remarkable increase in the speed of static memory circuit devices using MO8 field effect transistors. In conventional static type memory circuit devices, information from a memory cell is conducted through a switching transistor (transfer gate transistor) that is turned on and turned off by a signal selected by the address input on the Y side to the data line. It was common.

This method has the advantage that the area of the cheer 1 is smaller than the method of inserting a sense amplifier every digit 41 (biy) 11 ). However, the 1981 International Solid State Circuits Conference (
IS8CC) Digest of Technical Pavers
Ersu Vol 24. As described in PI3, significant improvements in speed can be achieved by including differential amplifiers in the spar lines.

FIG. 1 shows a conventional memory circuit. Here, memory cells 100 to 1o2. It includes differential amplifiers 109 to 111 for amplifying the digit line signals of each digit line 103 to 108 degrees, and a data bus "12el13*data out amplifier 114. Conventional MOS transistors are shown in FIG. As shown, the source 201 Th and drain 202 regions are symmetrical with respect to the gate electrode 200, and the gate electrode and the source and drain regions partially overlap, so there is a couple between the gate electrode and the drain region. Capacity exists.

This capacity can be an advantage depending on how it is used, but it is generally a disadvantage. The latter case also applies when used in the differential amplifier shown in FIG.

There is a distance of 115°116.11 between the gate electrode of the transistor of the differential amplifier connected to the digit lines 103, 105, 107 and the drain region of the transistor connected to the data bus.
Likewise, there is a couple capacitance of 118,119°120 between the digit lines 104, 106°108 and the data bus 113. A certain row line xi.

When 121 is selected, the switch transistors (transfer gate transistors) of memory cells 100 to 102
is ONI, and each memory cell information appears on each digit line. The information of the memory cells connected to this row line is the same, for example, one column line 103, 105°107 is all high (c).
The other girder line 104, 106°108 is
Suppose it was. In this state, when a transistor of a differential amplifier connected to YI, selected by the address signal on the Y side, is turned on, the data line 112 tends to go low. However, since Yi-H to YN are not selected, the data bus 113 tends to go low due to the couple capacitance between the remaining digit lines and the data bus.

The individual couple capacitance value is small compared to the parasitic capacitance attached to the data bus, but when all the memory cells have the same information as in this example, the value of the couple capacitance becomes so large that it cannot be ignored. Therefore, both data buses 1 of the information to be read are
The signal difference between 12 and 113 is reduced by the above couple capacitance, or in some cases is reversed, leading to a delay in read speed and malfunction. To solve this problem, we inserted a transistor to separate the transistors connected to the data bus and the digit line, as shown in Figure 3.
- A selection method using a Y selection signal is used.

However, this method has the disadvantage that the digit line amplifier becomes large. Therefore, it would be effective if a transistor with a small coupling capacitance between the gate electrode and the drain region could be used only where necessary.

A first object of the present invention is to provide a transistor in which the coupling capacitance between the gate electrode and the drain region can be reduced without significantly changing the conventional transistor manufacturing technology.

In the transistor according to the present invention, at least the drain region has an offset structure with respect to the gate electrode, and the source region and the drain region are geometrically asymmetrical with respect to the gate electrode. Furthermore, this transistor has an asymmetrical electrical characteristic, and if the source and drain are interchanged, the value of the current flowing through this transistor differs.

A second object of the present invention is to provide a semiconductor integrated circuit device having both the above-mentioned lifetime asymmetric transistor and a conventional geometrically and electrically symmetric transistor.

A transistor according to an embodiment of the present invention is shown in FIG.
(C) Explain using t-. As shown in FIG. 4(II), a gate oxide film 401 is formed on a P-type S1 substrate 400.
t After forming the gate electrode 402, arsenic ions are implanted at an angle of θ with respect to the vertical and pressed in by high-temperature heat treatment, as shown in Fig. 4(C).
This results in a geometrically asymmetric table transistor as shown in . As shown in FIG. 5, the ID-VD curves when the region 404't drain and 405 are used as the source and conversely when the 404k source and 405 are used as the drain, are different 0 curves 500 in the former case. Curve 501 is the latter case. The transistor shown in FIG. 4(C) is made of polysilicon (SI) 402 i as shown in FIG. 4(b).
Arsenic ions may be implanted after forming the poly-Sl
When 402 is heavily doped with phosphorus, the oxide film formed around the poly-Si is thicker than the oxide film formed on the 8i substrate, making it easier to fabricate an asymmetric transistor.

The dotted line 502 in FIG. 5 corresponds to a transistor that is geometrically symmetrical, the source/drain is not in an offset structure with the gate electrode, and the gap and gap between the source and drain are the same as L in FIG. 4(C). This is an IDVD curve. Of course, there is no difference even if the source and drain are replaced.What is noteworthy is that the curves 502 and 500 are almost the same, with only a slight difference in the saturation region. That is, when the region 404 in FIG. 4(C) is used as a drain, it is possible to obtain the same transristor ability as a symmetrical transistor.

At what level of offset Los between the gate and the region 404 shown in FIG. 4(C) becomes asymmetry occurs? In Figure 6, the distance between source and drain is 1 μm,
The gate oxide film is 5001. FIG. 6(b) shows a transistor with a channel width of 100 μm.

Drain current ll5 measured with the connection shown in (C)
It, * K-) 1ffl value as pressure Vte t-Vy* f
) The differences ΔI and ΔVte are plotted against the offset amount Los. For ΔF, when Los becomes 5ooX, which is equal to the gate film thickness, the current asymmetry becomes 0 again.
, it can be seen that asymmetry in the gate threshold voltage begins to appear around 15μ. The capacitance value between the drain and gate electrode is LO8
= 0.15μ, it was measured that the force in the case of Fig. 6(b) is 20% smaller than in the case of Fig. 6(C)9.

In this way, by using a transistor having a structure in which only the drain and gate electrodes are off and set, the coupling capacitance between the two can be reduced, and the transistor performance is not impaired. Further, as explained with reference to FIG. 4, a transistor having an offset amount can be formed by simply implanting source and drain impurities obliquely, and this can be used in the differential amplifier shown in FIG.

By using a transistor with source and gate electrodes, the current capability and gate threshold voltage can be easily formed. can be formed into Furthermore, it is also possible to separately provide a transistor whose source and drain are implanted diagonally and a transistor whose source and drain are implanted vertically, and use these transistors as required.

[Brief explanation of the drawing]

Figure 1 is a memory circuit diagram showing the necessity of using the asymmetric transistor of the present invention, Figure 2 is a conventional symmetric transistor,
Figure 3 shows a beam line differential amplifier that is an improved version of Figure 1, and Figure 4 (a).
) to (C) are diagrams explaining the asymmetric transistor of the present invention, FIG. 5 is an ID VD curve, and FIG. 6 (a) to (C)
FIG. 2 is a diagram showing the dependence of current and gate threshold voltage on the amount of offset between the gate electrode and the source or drain. 109-111...Sense amplifier, 100-1
02-3 ( 'i-+ plan・'3 figure 4ρ3 蓼couve

Claims (1)

[Claims] 1. A semiconductor device comprising a field effect transistor in which a gate electrode and a source or drain region have an offset structure, and the source and drain regions are arranged asymmetrically with respect to the gate electrode.