JPS5847889B2 - semiconductor logic circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flip-flop based on a new operating principle, and in particular to a frequency divider circuit with a minimized number of gates.

Many frequency divider circuits have already been known.

Some typical examples include the J-K flip-flop type, the master-slave flip-flop type, and the torque flip-flop type.

Many of these are quite large numbers of NAND, NOR, IN
For example, a 12L toggle flip-flop typically requires 6 NAND gates.

These dividers are implemented using integrated circuits, and in systems such as electronic watches that require low power and use many frequency dividers, each frequency divider operates with particularly low power, and the frequency divider 1
The area occupied by each piece must be small.

If the number of gates that make up an individual divider is small, it is possible to not only reduce the area occupied by the divider, but also reduce the power consumption of the divider as the sum of the power of each gate. It is.

An object of the present invention is to provide a frequency divider configured with a minimum number of gates by adding new functions to gates or flip-flops.

Another object of the present invention is to improve the functionality of logic circuits, reduce the number of gates, and reduce power consumption by using gates or flip-flops with new functions.

The frequency dividing circuit according to the present invention includes first and second flip-flops FF1 and FF2.

The first flip-flop FF1 is a Bs flip-flop that controls the direction of collapse when two inputs simultaneously change from a dual-input state to a no-input state, and the second flip-flop FF2 is a normal RS flip-flop.

Inputs of a certain predetermined frequency are applied in phase to two inputs of the first flip-flop FF1.

The two outputs of the first flip-flop FF1 are respectively connected to the two input terminals of the second flip-flop FF2.

The direction in which the first flip-flop FF1 falls when changing from dual input to no input is determined.

FIG. 1 shows the basic concept of the branching device of the present invention, and the broken line in the figure shows the above-mentioned control path.

In order to control the direction in which the first RS flip-flop FFI falls down when it changes from a dual-input state to a no-input state, either the switching speed of the two NAND or NOR gates that make up this flip-flop can be controlled. All you have to do is control it so that one is faster than the other.

Let the two gates be ■1 and v2, and if v1 has a faster switching speed than v2, V1 will output an output signal faster than v2, and due to the cross-coupling of V1 and v2,
Since the output of V1 suppresses the switching of v2, v2 ends up with no output signal, and finally, 2 becomes active and 2 becomes inactive and becomes stable.

'Figure 2 shows the concept of the present invention in an injection type logic element ■2L
(Integrated Injection Log
ic) is shown as a concrete equivalent circuit.

In the figure, two cross-coupled transistor pairs T1 and T2,
T3 and T4 each constitute an RS flip-flop.

Constant current sources ■1, ■2, ■3, and ■4 are T1 and T2, respectively.
, T3, and T4.

The output Q of the fritz flop FFI consisting of T1 and T2,
, Q, are connected to inputs R2 and S2 of flip-flop FF2 consisting of T3 and T4.

? 1, ■2 is the current value 11. 12 is a current source controlled by the state of flip-flop FF2, and its control is such that Q2 is ``'F-]''.Q2 is tt L
When pt, 1 t<t 2 tQ2 is "L", and when Q is ゜H'', i1>12.

The presence of a control path is indicated by a broken line in the figure, and a bar is added next to the constant current source symbol to indicate that the current source is controllable.

FIG. 3 shows an example in which the circuit of FIG. 2 according to the present invention is implemented in an L2L structure.

That is, facing the injector 1, the NPN I-transistors T1 and T3, and T2 and T4 are arranged adjacent to each other.

Region 2 is the emitter of each NPN l-transistor and at the same time the base B1 . This is the base region of a PNP transistor whose collectors are B2, B3, and B4, and whose emitter is the injector 1.

This PNP transistor has T1. It functions as a constant current source connected to each base of T2, T3, and T4.

Cll, C12, C21, C22, C31. c.
32, C33, and C41 indicate the collector regions of each NPN transistor, respectively.

Each collector region is provided on the inner main surface of the corresponding base region.

Thick line segments indicate metal wiring for connecting each region.

Each part of the metal wiring is marked with a symbol corresponding to that shown in FIG.

In the structure of FIG. 3, the minority carriers injected from the injector 1 pass through the region 2 to the base B1 of the NPN transistor. B2. B3. B4l was captured.

Now Q2="}T". In the state of Q=”L I+, φ
, q are both grounded.

At this time, Bl, B2 are ``L'', B3 is ``LtlB4
is "H".

Minority carriers injected from injector 1 are in region 2
through B1, B2, B3. Captured by B4, but B1
The minority carriers injected into the boundary region 213 between and B3 are
Since both B1 and B3 are at the It L 91 potential, it flows equally into both bases.

However, for the current flowing into both bases through the boundary region 224 between T2 and T4, B2 is "L" and B4 is "H".
tt, the current flowing to B2 is larger than the current flowing to 84.

Therefore, the total current flowing from injector 1 to B1 is i1
, B2 is 11 times i2.

That is, when Q2-H and Q2-L, i1>i2.

Similarly, when Q2 −L +Q2=H, 1 1>
1 2.

3 (here, the second flip-flop F
Corresponding to the level of potential of the base of the transistor constituting F2, for example, base B3, the current flowing from the injector 1 to the base B1 of the transistor of the first flip-flop FPl adjacent thereto increases or decreases. , B3 as the emitter, 213 as the base, and B1 as the collector, the current reversely injected from B3 to B1 increases or decreases.

B1 has an inverse relationship with the potential level of B3, so B2
The current flowing into B1 increases and decreases in the opposite direction to B1.

Therefore, the inversion direction of the first flip-flop FF1 is controlled depending on the switching speed of the transistors T1 and T2.

By the way, at this time, the collectors C12 and C22 of the transistors that connect the output of the first flip-flop FF1 to the second flip-flop FF2 end up repeating transistor operation and diode operation.
This is not necessarily an indispensable phenomenon.

In addition, in the case of a 12L structure like this example, the first
Since current is supplied to the flip-flop FF1 by the injector 1 as a constant current source, one of the multi-collector transistors C12. C22
Even if Cl repeats transistor operation and diode operation, the other transistor Cl used for cross-coupling
1, has almost no effect on the operation of C21, and thus on the inversion direction of the first flip-flop FF1.

Next, the present invention will be explained by taking as an example the operation of the circuit shown in FIG.

First, assume that Q2'=H and Q2=L.

At this time, R2-L, S2=H and 1 1 < 12
It is.

Since the operating speed of l2L is proportional to the inflow current, when the input φ, of flip-flop FF1 changes from both grounded state to both open state, transistor T2 starts conducting faster than T1, and the conduction of T2 is crossed. As a result of the wiring working to prevent conduction of T1, Q1=H, Q
, = L and becomes stable.

This reverses the state of the flip-flop FF2 consisting of T3 and T4, so that Q2 = L + Q2 = H.

Next, if Q2 = L + Q2 = H,
R2=H, S2=L, and i1>t2.

child? When φ and ψ change from both grounded state to both open state, T1 starts to conduct faster than T2, and as a result, it becomes stable at Q1 = L + Q1 ""H.

This reverses the state of flip-flop I''F2, making Q2=H and Q2=L.

If φ and f change from both open states to both grounded states at the same time, T
1, T2 becomes non-conductive, but this does not change the state of FF2.

To summarize the above, in the circuit shown in Figure 2, when φ and f change from both grounded states to both open states at the same time, FF2 changes state, and φ and φ' change from both open states to both grounded states. When this happens, FF2 will not change its state.

Therefore, φ, f, Q2, Q2 change as shown in the timing diagram of FIG. 4, and the circuit of FIG. 2 operates as a frequency divider.

The multi-collector outputs Φ and Φt that are in phase with Q2 can be given as frequency-divided outputs, which can be input to the next divider.

In the above operation, when the state of FF2 is switched using the state change of FF1 determined by the magnitude relationship of [1 and 12 as input], the magnitude relationship of i1 and i2 is reversed;
This reversal of the current value relationship itself is the FF. In order to prevent oscillation, it is necessary to avoid inducing new state changes.

For this purpose, it is necessary that the difference in current value is not extremely large, and that the current amplification factor β of T1 and T2 is sufficiently large.

In other words, the current value controlled by the state of FF2 is +
It is necessary that β1 2> 1 1 when 1>+2 and β1 1> 1 2 when i2>i.

Next, another embodiment of the present invention is shown in FIG.

Figure 5b is a sectional view taken along line X-X in the plan view of Figure 5a.
Shown below.

Part of base area B3, B4 of T3, T4 B31・,B
41 bypasses the lower part of the injector 1 and connects T and T, respectively.
, T2 near the base regions B1 and B2.

Minority carriers injected from injector 1 are T1,
flows into the base region of T2, and the respective base current 11
+12, but part of it is captured by B31 and B41.

As in the case of FIG. 3, the magnitude of the captured current is controlled by the potentials of 831 and B41, that is, the state of flip-flop FF2 consisting of T3 and T4.

Q2-”}J 29 , q2=”L I+? 3
1 is ``L'', B41 is ``H91, and the above-mentioned shunt distribution is that B31 is larger than 841, and therefore the base current l1 of T1 is smaller than the base current 12 of T2<+1
<12.

Similarly, Q2♂LB tQ2 =? When T H j+, 1 1 > 1 2.

Therefore, the structure of FIG. 5, like that of FIG. 3, corresponds to the circuit of FIG. 2 and operates as a frequency divider.

FIG. 6 shows yet another embodiment of the present invention.

Q2 = ``H'' + Q2 -''L'' That is, if the base of T3 is ``L I1, then the Shoratsuru carrier injected from the injector facing the base of T3 will be T3.
flows into the base of.

However, if the base of T3 is "H", some of the minority carriers that have flowed in will be re-injected and
It is captured by the protrusion B11 of the base B1 of T1 and added to the base current i1 of T1.

This also applies to T2 and T4.

Therefore, Q2=f+ i, jl, Q2=? lH
"' then i1 < 1 2 * Q2 -" L
"+Q-"H', then +1>12.

This is the same as in FIG. 3, and the structure in FIG. 6 provides a circuit equivalent to that in FIG. 2, operating as a frequency divider.

Although the invention has been described in terms of a splitter, the basis of its operation is I{. The two-man power of S flip-flop,
When both inputs are applied and both inputs are turned off at the same time, the RS flip-flop is configured.
By controlling the magnitude relationship of the switching speeds of the two gates, the direction in which the RS flip-flop falls can be arbitrarily set.

In the case of 12L, the current flowing into the input region of the inverter corresponding to each gate is controlled by changing the potential of a region of the same conductivity type adjacent to the input region.

This method is applicable not only to frequency dividers but also to general flip-flops. It can also be applied to logic circuits, improve the functionality of each, and reduce the number of gates and thus power consumption.

As is clear from the above description, the present invention can be applied to general flip-flops or logic circuits to simplify the circuit and reduce power consumption, and is useful for increasing the functionality of logic circuits. be.

The present invention is particularly applicable to frequency dividers, and its effects are significant.

That is, the number of gates used in the frequency divider can be kept to a minimum, and basically it can be constructed from two RS flip-flops.

If the frequency divider according to the present invention is composed of ■2L, the frequency divider is only 4L.
It is constructed with one inverter and can be constructed with an extremely small footprint.

Therefore, if applied to devices that frequently use frequency dividers, such as ICs for watches, it will be extremely effective in reducing chip size and frequency division power.

[Brief explanation of the drawing]

Figure 1 is a basic conceptual diagram of a frequency divider using the RS flip-flop according to the present invention, and Figure 2 is a diagram showing the basic concept of a frequency divider using
Fig. 3 is an equivalent circuit diagram when using IL, and Fig. 3 is a plan view showing the first configuration example in this frequency divider IIL structure.
The figure is a timing diagram for explaining the frequency division operation of the circuit shown in Fig. 2, and Figs. 5 and 6 are plan views showing second and third configuration examples in the ILL structure of the circuit shown in Fig. They are a figure and a sectional view. Note that the same symbols are attached to corresponding parts in each figure. In the figure, FFI and FF2 are RS flip-flops, ■1
, 1 is a control means, T1, T2, T3, and T4 are NPN transistors, 1 is a P-type injector region, and 2 is an N-type region.

Claims (1)

[Scope of Claims] 1. A first flip-flop configured by a cross-coupling of first and second inverters; a flip-flop configured by a cross-coupling of second and fourth inverters; the output of the first flip-flop is input; A first flip-flop constituted by two common-base transistors having their emitter-collector connected to respective inputs of the second flip-flop, the first and third inverters, and the second and fourth inverters, respectively.
and a second inverter input current control means, which controls the input current and switching of the first and second inverters when each input of the first and second inverters simultaneously changes from a dual-input state to a no-input state. A semiconductor logic circuit device in which the magnitude relationship of time is controlled by the common base transistor according to the logic state of a second flip-flop. 2. The first, second, third and fourth inverters are arranged in an integrated injection logic structure, and the input current control means is arranged so that the respective input regions of the first and third inverters facing the injector are connected to each other. Comprising a composite structure base-grounded transistor obtained by arranging the respective input regions of the second and fourth inverters in close proximity to each other and facing the injector;
A first effect in which a portion of the current injected into each input region of the inverter changes depending on the potential of each input region of the third and fourth inverters, and of the first and second inverters by causing one or both of the following effects: a second effect in which the reinjected current to the second inverter changes depending on the potential of the input regions of the third and fourth inverters; The semiconductor logic circuit device according to claim 1, wherein the magnitude relationship between input current and switching time is controlled.