JPS5847304A - Phase processing circuit - Google Patents

Abstract

PURPOSE:To obtain a phase processing circuit which is suited to an operation with a low lever of voltage, by using a differential amplifying circuit comprising the 1st-3rd and the 4th-6th transistors having the emitters connected to the 1st and 2nd current sources and a current mirror circuit. CONSTITUTION:The emitters of transistors TRQ14-Q16 are connected to a current source IS1; while the emitters of TRs Q14-Q16 are connected to a current source IS2. The DC bias V1 and input signals VIN1 and VIN2 are applied to the bases of TRs Q11 and Q16, and the collectors of the TRs Q11 and Q16 are connected to a power supply VCC. The bias V1 is applied to the TRs Q13 and Q15 plus to a terminal 21a of a phase shifting circuit 21, and an input FM signal is applied to the other terminal 21b of the circuit 21. The signal supplied from a terminal 21c is applied to the bases of the TRQ12 and Q14. Thus a differential amplifying circuit is formed. The output of the common collector of the TRQ12 and Q15 is connected to the output side of a current mirror circuit CM25 via a circuit CM23. The output of the common collector of the TRs Q13 and Q14 is applied to the input side of the circuit CM25 via a circuit CM24. Then the difference of the output of the TRs Q12 and Q15 and the outputs of the TRs Q13 and Q14 is delivered from an output terminal 26.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase processing circuit suitable for use in FM detection circuits and the like, and is designed to achieve low voltage operation.

Recent FM detection circuits use a mesyl dI)ys type differential amplifier as shown in Fig.
A (Q11 turtle dratur) detection circuit is often used. However, this circuit has a configuration in which many transistors are connected in series (three transistors in FIG. 1) between the power supply line and the ground potential, so it is not suitable for low voltage operation. In Figure 1, Ds *
D, are transistors Qt-Q*,) transistor Qs*Q4,) transistor Qse, respectively.
Qs) is a differential amplifier consisting of each pair.

2:1. IJI is the 11th second and third current mirror circuit, and 14 is the capacitor? The phase shift circuit formed by the Ct*Css coil L1 is an i-double/f lance-type differential amplifier, which includes first, second, and third differential amplifiers Dl s
The current collector current path formed by Ds*Da and between the power supply 2-in J5 and ground potential of this circuit is a constant current source! 1 is used as a common current source. Vl,
V.

V3 is a DC/IR insulator source, vINI" IN2
is the input FM signal. Further, a capacitor 08% resistor R1 is connected to the output terminal 16.

In the above FM detection circuit, if the output signal of one output terminal 16 is I, and each transistor has the same characteristics, when there is no signal, Ic3'Ic4'Ias'' cd is the transistor Qs e Q4 * Qs eQ
− collector currents, 1. is a constant current source 1. The fact that the current flowing in y = 0 means that a state of equilibrium is maintained.

Next, the operation when a signal is present will be explained.

Now, to simplify the explanation, a case of square wave complete switching operation will be explained.

By the way, the transistor Q10 base input signal is vll
If the pace input signal of transistor Qs is V□, then vss = Vl +V.

Vl4 =v1 +vIW2 ” ■1 ””” vI
M.

The input signals V and V□N2 are set to have opposite phases.Next, the pace input signal of transistor Qs is set to Vl3, the pace input signal of transistor Q4 is set to 114, the pace input signal of transistor Qs is set to Vl5, and transistor q is set to When @ pace input signal is applied at Vl6, v15=v,, = v, +v,,.

Vl4-■, 6=v.

*VIH3u) is the inter-pace signal of transistors Qs and Qa.

By the way, to become "as" Is, vII > V
12 and when V□>v', transistors Ql-Ql turn on.

Next, in order for X =
The ToD transistors Q* and Qa are turned on.

Next, in order for Ie5==I, when V,1<Vl2 and V□>vs, the transistor Q oscillation eQ* is turned on.

Then 1.6=x! , when V, , < v, 2 and V □ < V s,
Transistor Qs-Q@ turns on.゛However, “as”
``cd''■c!!''``cd'' is the collector current of the transistor Qs-#Q4*Qs/Q-, respectively.

The operating waveforms obtained under each of the above conditions are shown in Figure 2 (a'
・)% As shown in Fig. 3 (a to ・), Fig. 2 shows the current system g on the transistor Ql side.
The figure shows the current system on the transistor Qs side.

FIG. 2(a) shows the pace input signal C of transistor Q1.
v*, = V t + Vx, y) Figure (b) shows the voltage waveform and shows the waveform changing in the positive and negative directions around 1 reference/each Ias.
The voltage waveform of the pace input signal (V, 5==V□) of Q@ is set, and a phase shift of 90' with respect to the input signal is set. (e) of the same figure shows the current waveform of the collector current I04 of the transistor Qs, and (d) of the same figure shows the current waveform of the collector current I04 of the transistor Q4.

Combined collector current (Ie
3+Xe6) waveform. Similarly, FIG. 3(1) shows the pace input signal (V, 2=Vl +
V,,2=v,-v,,, ) Chisel pressure waveform, Figure /b) is the pace input signal of transistors Q4 and Q6.

r Figure (e) shows the collector current of transistor Qs, Figure (d) shows the collector current of transistor Q, Figure ()
is the combined collector current of transistor Q 4 +Q s.

The waveform shown by the solid line in Figures 2 and 3 is when the frequency f of the input signal is f''/o, which is the FM center frequency. As shown in the figure, if Toυ and deviation are smoothed with a duty of 50s, the DC level of the output signal becomes zero, and the zero-order frequency f becomes low.
In the case of f = io - Δf, a phase shift as shown by the dotted line in Figures 2 and 3 is obtained, and the output is as shown in Figure 4 (b).
The output waveform is shown in . Therefore, the output DC level DC1 at this time changes in the negative direction. If the frequency f is even higher, f=f・10Δf, then
The phase shift shown by the dashed line in Figs. 2 and 3 is obtained, and the output waveform is as shown in Fig. 4 (@). Therefore, the DC level of the output at this time D
C becomes the turtle that changes in the positive direction. As shown in Part B, the output level changes depending on the FM modulation of the input frequency.
The 7M detection output is a continuous output of this change.

As mentioned above, the conventional circuit described above is not suitable for low voltage operation because it has a large number of transistors connected in series between the power supply line and the ground.

The invention was made in view of the above circumstances, and its purpose is to reduce the number of transistors connected in series between the power supply twin and ground, and to provide a phase processing circuit suitable for low voltage operation. do.

Embodiments of the invention will be described below with reference to the drawings.

In Fig. 5, transistors Q11 and Q13-QIB
The common emitter of the first current source 1. , and the common emitters of the transistors Qxa* Qss* Qs are connected to a second current source "m2."

Current source 11''!The current flowing through a2 is Isl' 11
If it is set to 2, "sl"ls" is set to 2.

First and sixth transistors Qll
NI'l vl)12 is input. Here y =
-VIHl and are in opposite phases to each other. Direct w2 current/4ias v1 is the third and fifth transistor Qs@
Added to the pace of nQ15 and capacitor C
It is also added to the terminal 21 of the phase shift circuit 21 constituted by the 1*Css coil L1. The input FM signal is applied to the other terminal 21b of this phase shift circuit 21, and the FM signal via this phase shift circuit 21 is output from the output terminal 21e to the second terminal 21b.
, the fourth transistor Qxs, Qta'. Here, the first and sixth transistors Q*t
The collector of eQt is connected to the power supply line 22.

The output of the common collector of the second and fifth transistors Q*seQMi is connected to the output side of the third current shifter circuit 25 via the first current shifter circuit 23 as an output circuit. It is led out to the output terminal 26. Also the third
, the output of the common collector of the fourth transistor Q1seQ*a is applied to the input side of the third current electric two circuit JI5 via the second current electric two circuit 24, and this output side, the tb output terminal 26 Output terminal 26 led out to
is connected to a capacitor am for carrier removal and a direct current I+earth Vl via a resistor R1.

The FM detection circuit of the invention is constructed as described above, and includes the first,
The sixth transistor Q*Qt@ functions as an input circuit, and input FM signals having mutually opposite phases are applied to each E. Also second. The pace of the fourth transistor QxseQx4 has an FMgs which is 9 Q” ahead of the input FM signal when the input FM signal is at the center frequency (unmodulated).
The number is entered. As a result of this, an FM detection operation is obtained, and the output current I*a @1 of the output terminal 26 and the second current ζ2- are derived as the difference between the two input currents of the circuit.

Figures 6(a) to (e), Figures 7(a) to (・), and Figures 8(a) to (c), operating signals shown to explain the FM detection operation of the above circuit. FIG.

Now, to make the explanation easier to understand, we will use a square wave complete switch,
The operation when the proboscis is operated will be explained.

When there is no signal, I,, = 1.2 = I,
Transistor Qll~Q1@, current 19-circuit'
Diode Q1 configuring J e J 4 #25.
.

Assuming that Ql, Qll, F transistor Qt@eQ*ejQ, etc. have the same characteristics, and ignoring the pace current, the pace voltage lines of each transistor Q11 to Ql- are equal to Vs. Therefore, lo-Xca-Ial torture-(
Ic2”as)”@5”c4)=('!+!-x)
−< −r +−x )=.

3 纒1 am2 asl 3@2. Note that I,, II. 5 e Ic4 * IC
l3 e I, 6e I0, 2 are each transistor QCs
a Qtse QsaeQts-Qt·, means the collector current of 9 ports.

and ζ~transistor QsteQt*5Q1s*Q*a
e Qsse Qxs input signal ■3. .

vl2 m VIJS e VH4* Vms e V
Assuming H4, VH=V s+VIHI V14=v1+vlW2”vl-vImrl-v
mz “vms”” 1+ VswsvlB-vl
=v1. vIMM is the FM signal after the input FM signal passes through the phase shift circuit 21.

Therefore, Ic2 becomes 1.2e=1 only when v, <vt"t' and vl12>vl.

"am is Vll < V s "1" L Ka is also V,
, (I□, g=I only when V, O.

Ic4 is vl6<v, “t” and v,4>v 1
Ic4=I only when .

vms becomes Ic5 =I only when v,6<vt and v,4<v.

The above operation waveforms are as shown in FIGS. 6 and 7.

FIG. 6(a) shows the pace input signal V of the transistor Qtt.
, and (b) of the same figure shows the pace input signal v12 = vl4 of the transistors Qll and Ql4. And the same figure (
e) is the collector current xo1 of the transistor Q1m (
d) is the collector current "a2" of the transistor Q2.

Also, in the same figure (·) is the common collector current I of the transistor QsssQsi. +Ies. Similarly, Figure 7 (#L)
is the pace input signal v, 6 of Torafuji No. 1291, the same figure (
b) is the pace input signal v of transistor Qll-Q14
12=v14. And (e) in the same figure shows the collector current of transistor QH! , 5° Same figure (11 is the collector tfi Ic4 of transistor Q14.
) is the common collector current I, , 1Ic4 of the transistor Q as eQ 14.

In FIGS. 6 and 7, the waveform shown by the solid line is when the frequency f of the input signal is f=f* and is the FM center frequency.
The output waveform at this time has a duty of 50% as shown in FIG. 8(-), and if this is smoothed, the direct level of the output signal becomes zero if the intermediate and negative signals are removed. Next, when the frequency f is low, ff - Δf, the sixth
Figure, Figure 7 - The dashed line shows the 7th shift.

is obtained, and the output becomes the output waveform shown in Fig. 8(b). Therefore, the DC level of the output at this time is DC1
changes in the positive direction.If the frequency l increases and f = fo + Δf, a phase shift as shown by the dotted line in Figures 6 and 7 will be obtained, and the output will be 8
The output waveform is as shown in Figure (c). Therefore, the output DC level DC at this time changes in the negative direction. In this way, the output level changes in accordance with the FM modulation of the input frequency, and the 2M detection output is the result of this continuous change. The conductor y f O@ removes the intermediate voltage (2f at the output end), and the resistor R1 serves to convert the current output into voltage.

Particular attention should be paid to the circuit of the present invention described above:
Excluding the current source, there are only two elements (transistors) in series between the power supply line and the ground potential terminal.As a result, this circuit has the ability to operate with a very low voltage power supply. It is ideal for reducing power consumption and integrating circuits. Furthermore, the level of the output average DC current does not vary depending on the presence or absence of the FM signal (when no modulation is performed). Therefore, the output of φ and K is also suitable for use in automatic frequency control AFC circuits. (I + Ic,) and (I,, + I,) in the differential amplifier circuit part
Since the current difference of 4) is outputted as 2, the detection efficiency is also high.

Furthermore, in this circuit, as shown in FIG.
ll Qtse Qtse If it is made larger (for example, twice) than that of Qts, it is possible to further reduce the detection output distortion. This can be understood from the fact that when considering the internal distortion of a transistor, the degree of current dependence increases in the transistor part that has a balanced operation relationship.In the above explanation, the FM detection circuit was explained. 1st between the paces of QIIIQI・
It can also be applied as a circuit that adds a second input signal to the input signal of the transistor QllllQsa and a common pace of the transistor QllllQsa, and obtains the phase detection and output of both signals. ), there is no fluctuation in the output average level even when there is no signal, the detection efficiency is high, and it can operate at a particularly low voltage compared to conventional products. An effective phase processing circuit can be provided.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional FM detection circuit, and Figure 2 (-~(
e), Figure 3 (a) ~ (@), Figure 4 (a) ~ (-
) is an operation signal waveform diagram shown to explain the operation of the circuit in FIG. 1, and FIG. 6 is a circuit diagram showing an embodiment of the invention.
Figures 6 (&) to (・), Figures 7 (a) to (・), and Figure 8 (a) -; (q) are operating signals shown to explain the operation of the circuit in Figure 5. The waveform diagram and FIG. 9 are diagrams partially showing another embodiment of the present invention.
) Transistor 1.21・°・phase shift circuit, 2:1.24@
25...Current filter circuit, I m, * I a
2...Current source / Applicant's representative Patent attorney Takehiko Suzue Figure 2 (c) ``--'' 0 (d)ri /7- ・ 0(e)-4
-1-1 λ-〇Figure 3 (c) F'':4s',,0 (d)''=Shi1s t-'q O5 (e) ``L-bot beat-cho]2''0 Figure 6 Figure 7

Claims (2)

[Claims] (1) The terminals of the first, second, and third transistors are connected to the first current source, and the terminals of the fourth, fifth, and sixth transistors are connected to the second current source. connected, said first
, the collector of the sixth transistor is connected to the power supply line, the @1 input signal is superimposed on the DC bias of Tsuru 1 between the paces of the first and sixth transistors, and the common pace of the second and fourth transistors. a second input signal superimposed on the first DC bias; and a second input signal superimposed on the first DC bias; A common collector of the transistor and a common collector of the third and fourth transistors; the difference between the outputs of the collectors is derived from the output circuit. A phase processing circuit characterized in that: (2) The first input signal is an input FM signal, and the second input signal is a signal obtained by passing the input FM signal through a phase shift circuit. Phase processing circuit according to section (3) The output circuit includes a first current t9-circuit connected to a common collector of the second and fifth transistors, and a common collector of the third and fourth transistors. The output of the first or second current mirror circuit is applied to the input terminal, and the output of the second or first current mirror circuit is applied to the output terminal. 2. The phase processing circuit according to claim 1, wherein the phase processing circuit is a third current mirror circuit. ,