JPH1098339A - Amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplifier circuit obtaining an output, without the distortion of a waveform by perfectly symmetrical push/pull operation. SOLUTION: Through the use of the first and second transistors Q11 and Q 12 of npn-type, a first DC power source E11 is connected between the collector of the first transistor Q11 and the emitter of the second transistor Q12 and a second DC power source E12 is connected between the collector of the second transistor Q12 and the emitter of the first transistor Q11. An AC input signal is supplied between the respective base and emitter of the first and second transistors Q11 and Q12 as mutually reverse phase signal sources S11 and S12, and a load RL 11 is connected between the collectors or between the emitters of the first and second transistors Q11 and Q12 so as to allow the first and second transistors Q11 and Q12 to push-pull operate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a push-pull type amplifier circuit.

[0002]

2. Description of the Related Art Conventionally, as a push-pull amplifier circuit, as shown in FIG.
It is known that a load RL21 is driven by using n transistors Q21 and Q22. Input signals S21 and S22 having phases opposite to each other are applied between the base and the emitter of the transistors Q21 and Q22, and the transistors Q21 and Q22 perform a push-pull operation in which one is turned on and the other is turned off. One end of the load RL21 is connected to a connection point between the emitter of the transistor Q21 and the collector of the transistor Q22,
The other end is connected in series and connected to a connection point of DC power supplies E21 and E22.

FIG. 7 shows another push-pull amplifier circuit, which is a complementary circuit using a pnp transistor Q23 for one transistor Q22 in FIG.

[0004]

In the conventional push-pull amplifier circuit, the transistors that perform the push-pull operation are not completely symmetric when viewed from the load. That is, in the circuit of FIG. 6, the emitter of the transistor Q21 is connected to one end of the load RL21, and the collector of the transistor Q22 is connected to the load R1.
L21 are connected to the same terminal. Therefore, even if the characteristics of the transistors Q21 and Q22 are completely uniform, the load RL21
The impedance characteristics are different from each other, and this causes waveform distortion and the like. In the circuit of FIG. 7, two transistors Q
The emitters of the transistors Q21 and Q23 are commonly connected to one end of the load RL21.
Since the characteristics of Q23 are not usually the same, the output impedance is also different and the operation is not completely symmetric.

The present invention has been made in view of the above circumstances, and has as its object to provide an amplifier circuit capable of obtaining an output without waveform distortion by a completely symmetric push-pull operation.

[0006]

An amplifier circuit according to the present invention comprises first and second transistors of the same conductivity type having first and second main electrode terminals and a control electrode terminal;
A first DC power supply connected between a first main electrode terminal of the second transistor and a second main electrode terminal of the second transistor; a first DC electrode connected to the first main electrode terminal of the second transistor; A second DC power supply connected between the second main electrode terminals of the first transistor and the second main electrode terminal. The AC input signal is supplied to a control electrode terminal of each of the first and second transistors and a second main electrode. The first and second transistors are supplied in opposite phases between the electrode terminals, and a load is connected between the first main electrode terminals or between the second main electrode terminals of the first and second transistors. Are operated by push-pull operation.

In the present invention, as the first and second transistors, npn transistors (or both pnp transistors) are used if they are of the same conductivity type, that is, if they are bipolar transistors, and if they are MOS transistors, Both use n-channel MOS transistors (or both use p-channel MOS transistors). In the present invention, the first and second main electrode terminals respectively indicate a collector and an emitter in the case of a bipolar transistor, a drain and a source in the case of a MOS transistor, and a control electrode terminal in the case of a bipolar transistor. The base and the gate in the case of a MOS transistor are shown.

In the case of using a bipolar transistor, according to the present invention, a load is connected between the collectors or the emitters of the first and second transistors. That is, the output of the amplifier circuit is taken out as a differential output and supplied to the load. According to the amplifier circuit of the present invention, not only the element characteristics of the two transistors used are the same, but also the impedance characteristics seen from the load become the same, so that a completely symmetric push-pull operation becomes possible, and the amplification with a small waveform distortion becomes possible. Characteristics will be obtained.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a main configuration of an amplifier circuit according to an embodiment of the present invention, from which a DC bias circuit is omitted. In this embodiment, the first and second transistors Q11, Q11,
As Q12, an npn transistor having uniform characteristics is used. Connected between the collector of the first transistor Q11 and the emitter of the second transistor Q12 is a first DC power supply E11 whose collector side is positive, and the collector of the second transistor Q12 and the emitter of the first transistor Q11. A second DC power supply E12 having a positive collector side is connected between the second DC power supply E12.

The load RL11 has one end connected to the collector of the first transistor Q11 and the other end connected to the collector of the second transistor Q12. And the first and second
The input AC signal sources S11 and S12 having opposite phases are connected between the base and the emitter of each of the transistors Q11 and Q12. Actually, the signal sources S11 and S12 have a relationship between one input AC signal and an inverted phase signal whose phase is inverted.

The operation of the amplifier circuit of this embodiment is as follows. First, when the signal source is S11 = S12 = 0, the transistors Q11 and Q12 are both off, the circuit is in a balanced state, and no current is supplied to the load RL11. From this state, when the signal source S11 changes in the positive direction and the signal source S12 changes in the negative direction, the first transistor Q11 turns on soon and the collector potential starts to decrease. Following the decrease in the collector potential of the first transistor Q11, the emitter potential of the second transistor Q12 decreases, but the base of the second transistor Q12 is reverse-biased by the signal source S12. Kept off. As a result, the current supplied to the load RL11 through the path from the power supply E12, the load RL11, and the transistor Q11 increases. Signal source S11
Is inverted in the negative direction and the signal source S12 changes in the positive direction,
The potential of the collector of the first transistor Q11 rises,
When the potential of the collector of the transistor Q12 drops and the potential relationship is reversed, a current is supplied to the load RL11 through the path of the power supply E11 → the load RL11 → the transistor Q12. Since the transistors Q11 and Q12 are both npn and have the same element characteristics, and have the same impedance as seen from the load RL11, this amplifier circuit is a completely symmetric push-pull circuit.

FIG. 2 shows an embodiment in which the embodiment of FIG. 1 is slightly modified. This embodiment is the same as FIG. 1 except that the load RL11 is connected between the emitters of the first and second transistors Q11 and Q12. According to this embodiment, FIG.
A completely symmetric push-pull operation is possible on the same principle as that of the embodiment.

FIG. 3 shows an embodiment of a specific amplifier circuit based on the embodiment of FIG. 1 and including a DC bias circuit. In FIG. 1, the AC signal sources S11 and S12 applied to the first and second transistors Q11 and Q12 are shown as one AC input signal source S10 in FIG. To the transistors Q11 and Q12. First and second transistors Q11, Q12
The resistors R10 and R11 are connected between the base and the emitter to provide a self-bias. Also, the emitters of the first and second transistors Q11 and Q12 have different resistances so that they can have different potentials.
It is connected to a negative power supply V (-) via R13.

The input signal source S10 is provided as a differential input to a differential circuit composed of npn transistors Q13 and Q14 having emitters connected in common through DC cut capacitors C1 and C2 and input resistors R1 and R2. . The common emitters of the transistors Q13 and Q14 are connected to a negative power supply V (-) via a resistor R5, and the collectors are connected to the resistors R3 and R3, respectively.
Connected to the positive power supply V (+) via R4. The positive terminals of DC power supplies E11 and E12 connected to the collectors of the first and second transistors Q11 and Q12 are connected to the bases of the transistors Q13 and Q14 via resistors R8 and R9, respectively. Is to be given.

The output of the differential circuit, ie, transistors Q13,
The change in the potential of the collector of Q14 is caused by the pnp transistor Q1.
5, and are applied to the bases of the first and second transistors Q11 and Q12 via a buffer stage using Q16. The transistors Q15 and Q16 have their emitters commonly connected to a positive power supply V (+) via a resistor R6, their collectors connected to the bases of the transistors Q11 and Q12, respectively, and the collectors of the transistors Q13 and Q14 connected to their bases. Thus, a differential circuit is configured.

With such a configuration, it is assumed that, for example, the collector potential of the transistor Q13 rises and the collector potential of the transistor Q14 falls due to the input signal source S10. At this time, the transistor Q15 changes in the direction of turning off (the direction in which the collector current decreases) and the transistor Q16 changes in the direction of turning on (the direction in which the collector current increases). Thereby, the first and second transistors Q11, Q12
Self-bias between the base and the emitter by resistors R10 and R11 in the opposite directions, that is, the signal source S in FIG.
Biases of opposite phases corresponding to 11, S12 are applied.

The present invention is not limited to the above embodiment. For example, even if the transistors Q11 and Q12 in FIGS. 1 and 2 are replaced with n-channel MOS transistors T11 and T12 as shown in FIGS. 4 and 5, a completely symmetric push-pull operation can be performed similarly. Although not shown in FIG.
Also, a pnp transistor pair or a p-channel MOS transistor pair can be used as the second transistor.

[0018]

As described above, according to the present invention, two transistors of the same conductivity type are used, and these transistors are driven in an opposite phase to each other by an input signal, so that the differential from the corresponding main electrode terminal is obtained. With a configuration in which the output is supplied to the load, a completely symmetric push-pull operation is possible, and an amplification characteristic with small waveform distortion is obtained.

[Brief description of the drawings]

FIG. 1 shows a main configuration of an amplifier circuit according to an embodiment of the present invention.

FIG. 2 shows a main configuration of an amplifier circuit according to another embodiment.

FIG. 3 shows a specific circuit example including a bias circuit of the amplifier circuit of FIG.

FIG. 4 shows a main configuration of an amplifier circuit according to another embodiment.

FIG. 5 shows a main configuration of an amplifier circuit according to another embodiment.

FIG. 6 shows an example of a conventional push-pull amplifier circuit.

FIG. 7 shows another example of a conventional push-pull amplifier circuit.

[Explanation of symbols]

Q11: first transistor, Q12: second transistor, E11: first DC power supply, E12: second DC power supply, S
11, S12: input signal source, RL11: load.

Claims (1)

[Claims] 1. A first and second transistor of the same conductivity type having first and second main electrode terminals and a control electrode terminal, a first main electrode terminal of the first transistor, and a second transistor.
A first DC power supply connected between a second main electrode terminal of the first transistor and a first main electrode terminal of the second transistor;
And a second DC power supply connected between the second main electrode terminals of the first and second transistors. The second DC power supply is connected between the control electrode terminals of the first and second transistors and the second main electrode. The first and second transistors are supplied in the opposite phases between the terminals.
Wherein a load is connected between the main electrode terminals or between the second main electrode terminals, and the first and second transistors are operated in a push-pull operation.