JPS5846681A - Schottky junction type field effect transistor - Google Patents

Abstract

PURPOSE:To realize fine adjustment of characteristic by etching the entire part or by MESA etching the operating layer even after the electrode pattern is formed through the employment of such structure of FET to be formed at the contact surface between metal and semiconductor that the gate electrode is buried within the operating layer. CONSTITUTION:1, 2, 3, 5 are respectively semi-insulating GaAs substrate, operating layer consisting of N type GaAs, source and drain electrodes. The gate electrode 4 is buried within the operating layer 2 and 8 is the high resistance material GaAlAs provided in such a manner as covering the side of gate electrode 4. Moreover, an insulator 9 such as Si3N4 is provided in place of the high resistance layer 8, the operating layer 2 is formed thick in order to reduce the source resistance, drain resistance and only the gate electrode 5 is formed thin as the MESA structure 6.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor (hereinafter referred to as PIT) having a metal-semiconductor contact surface (hereinafter referred to as PIT
(abbreviated as)).

Figure 1 (2) shows a cross-sectional view of the basic structure of the existing Schottky type FRT.
The behavioral layer consisting of ll, +31i4) is this behavior jli
(Source and drain electrodes in Ohmig contact with 21, (
5; is located between these two electrodes +31+4j, and the active layer (2
) and a Schottky junction Y-shaped gate electrode.

The major factors that influence the characteristics of csJFgT with such a configuration are the source resistance (RB) between the source electrode (31 and the gate electrode) and the 41 pole (51), and the source resistance (RB) between the C drain electrode (4) and the gate magnetic pole (5). The drain resistance (R11) is the same as the characteristics (; is the resistance (R8) (Rtl) ik
'It needs to be as low as possible. For that purpose, as shown in Figure 11!2 (;, the thickness of 21 is large, and only the gate pole (5) is made thinner, making it a multiple structure 16), or as shown in Figure 5. As shown in Figure 4, the thickness of the active layer (21? thick), the semi-insulating fi41 directly under the gate polarization (5).
There is a structure in which a protrusion (7) is formed at i (11).
2) Thickness t is set equal to the basic structure shown in FIGS. 1-2 in order to keep the gate pinch-off voltage constant.

The operating principle of such a V-type IP j'r is that 1iEfl flows between the source and drain magnetic poles 131 (4).
lL'%: Active layer (214:: directly under the gate electrode (5)
The depletion layer formed (is controlled by 11, and therefore its current value is 1!!i (gate magnetic pole (5) of 21).
The thickness directly below and the carrier concentration C are basically determined.

Mafe KorJJ (/ Yoyitoki type FRTQJON,
The OFF operation is performed depending on whether the depletion layer OQ reaches the substrate (1) or not, and the voltage applied to the gate electrode (5) when the depletion layer (11) reaches the substrate (II) Vl>).In fact, this kind of FK'l'
1: Use C; In some cases, control of the drain 4c flow and this pinch-off voltage becomes important. This control method ultimately depends on the thickness of the operation ya t't+, its composition, etc., as shown in FIG.

Figure 2 and Figure II6 In any structure, after the active layer (2) is grown, the two gate electrodes (5) are provided, so the desired characteristics can be obtained while determining the characteristics during the manufacturing process. It was impossible to control whether the process χ was stopped at that point.

The present invention was made in view of such problems, and
This will be explained in detail with reference to FIG. 4 and subsequent figures. In Figure 4 ill
, (21, 131, +51 are respectively similar to those shown in FIGS. 1 to 5). The active layer consists of semi-insulating (lA9 substrate, N type L) & A8, and each source and drain electrode has one structure according to the present invention. The structure is basically different from the conventional structure (the difference is that it is a game).The four poles (4) are embedded in the active layer (21).

In addition, in this Figure 4C2 (8F is a high resistance material provided like the gate electrode (4ν side surface Y4*), for example ()a-
A/A8 is used.

Next, the structure shown in FIG. 4 will be explained in more detail by citing specific numerical values.

QIA showing resistivity Y higher than 107Ω-country! ! Board (1)
After depositing approximately 800 OA of molybdenum on top using electron beam evaporation, the gate electrode (4) is formed.
Leave the required width 1, for example, 1 μm, and remove it by etching using the Pukuzumae 7 Tenning method. 8 Next, insert it into a crystal growth furnace, and first make a resistance of 101 to 104 Ω - about the same as that of Japan.
To 1: 6 GK (X) AJ (1~x) - A8 (x+
o, s) A high-resistance material (8) is obtained by forming the material to the same thickness as that of Y motsupuden, and a carrier flkK1 is obtained.
~2X10 ts N-type tnaahs working layer'
0 (21v1500~2000A deposit. After the isthmus C2 on this working layer (2) (Ni source, drain (pole I; (14)
Formed using χAu+0 alloy, N1 and t. this'(
tii3114) Spacing is 5-42 m.

If the pinch-off voltage (Vp) obtained in this way is lower than the desired value (the second is the operating layer (2
The surface of 1 is etched little by little with NaOH-'8202 etchant.
vp)vJvrIi! ≠, which controls the value of l to -2, appears.

In addition, the high-resistance material is the floating capacity of the gate
i? I have one that reduces it.

5. Figure 11 shows another embodiment of the present invention, in which the one shown in Figure 44 has a configuration of t-1 and a source resistor (R8).

Drain resistance (to lower HD1g; thickness of 1 (2) Y thickness (instead C: operation 1-(2) 42 jfm (6) t- provided directly above gate 4 poles (4) It is.

The figure Ijs6 further shows another example Y, in which the fourth factor, the high resistance layer (the insulator (9)
is established. Concrete (2 is the substrate (11 on the surface)
281S-N41: After forming, gate forming area 1;
After opening the window, molybdenum is deposited to form the gate electrode.

Gate magnetic poles of desired shape (4
) and 811N4 insulator (9)! From then on, the active layer (21) and the source and drain electrodes t31 (41t' are shaded) in the same way as in the previous example.The thickness of the active layer (2) in this example g is 2600 to 2800 mm. With this, low source resistance (R8) and low drain resistance (RD) can be obtained.

FIG. 7 also shows an embodiment of the present invention, and in this embodiment C2, the source and drain IIL poles 131 (41) are also embedded in the operation @ 121. That is, the substrate (11
After growing 51gn4 (91Y) on top, open a window in the gate electrode area and form a primary 4: source, drain electrode!31(4
) array C gate electrode (5) is formed with molybdenum 1;
False conduction with N″” GaAl1 uav 4000
25L] 00iFffi, and thereafter operate similarly to the other embodiments to obtain 1i1121t-.

This is to obtain ohmic properties due to the tunnel effect.

Furthermore, FIG. 8 shows the example structure C in FIG. 7: In order to lower the source resistance and drain resistance, only the i-bi-operating layer (21t-thick, gate electrode 15) is made thinner as a t-metal structure (6). There is.

As mentioned above, the present invention C;
Since the gate electrode is buried in the active layer, it is possible to fine-tune the characteristics by etching the entire surface or the etching layer even after the electrode pattern is formed. Accuracy can be achieved.

I would like to add an explanation of the active layer crystal growth process that made the F1 structure possible, for example, Figure 9.
As shown, a gate electrode metal (4) such as molybdenum or tungsten is deposited by electron beam evaporation (6) on the main crystal surface (100) of a substrate (11) consisting of a semi-insulating GILA II crystal. Thereafter, a dry etching technique is used to form a strip Y with a width of about 710μ parallel to the axis <110> of the GILAI crystal.Subsequently, after a cleaning treatment, As0I!1-Ga-Ht thread vapor phase method or trimedel, Figure 9-11 is obtained by employing a pyrolysis method for organometallic materials using trimether aluminum and the like.
)+(0)4: As shown, the N-type G
&A8 &Grow crystals. 700 to the growth temperature at that time.
At ~750°C, the growth rate in the <100> axis direction of the crystal main surface is controlled in the range of 100~500^/11<i>H. At this time, the crystal growth starts from the exposed part of the crystal of the substrate (1), and if the height of the metal (4) is varied by 4 m, as shown in Fig. 9 (11).
As in 1, (i metal (4) membership starts laterally along the surface, and its lateral growth is about 20% of the longitudinal membership rate.
~50 times, so molybdenum is immediately CM type ()&A
The lateral member of the 8-crystal active layer (211 and 2 embedded, at this time 11112) can be up to about 50 tm. The electron mobility for this grown crystal operating layer (2) is 1 to
3 x 10 /as'recarrier thick fil- to 2 is about 5000 countries/V.8.O. The interface characteristics between the grown crystal operating layer (2) and the four-bridge metal (4), that is, the Schottky characteristics, are $11/.

Figure 2, ′! lN3 Fig. 6 The conventional one shown in Figure 6 and the current -
There was no significant difference in magnetic pressure characteristics, voltage-capacitance characteristics, etc. in C2.

As operation 111(2), GILAlg:, limit z<
, GIX)Aj'(1-43AI(X=α6~0.4)
Similarly, compound semiconductors such as Gl&P and InP can also be used, and the lateral growth of the crystal layer (2) is 110 m in addition to metals such as molybdenum, ailN41Al!2
It has been experimentally confirmed that the same phenomenon occurs on insulating materials such as oi.

[Brief explanation of the drawing]

Figures 1 to 6 are cross-sectional views showing the structure of conventional PBT;
The 1%4 factor to s8 diagram is a cut IT diagram showing the structure of the FIT of the present invention.
Figure i and Figure 9 are cross-sectional views showing the crystal growth process Y in the present invention, (1) is the substrate, (2) is the operation 19.15)
is a gate magnetic pole, (8) is a high-resistance material, (9) is a sticky material,
V is shown respectively.

Claims (1)

[Claims] 1) A game device made of a conductive material with a bifurcated substrate surface C.
a bridge, the surface of the substrate including the gate electrode (; an operating layer made of a formed semiconductor material; the operation 1-upper C; upper gate electrode Y; source and drain polarization deposited in a narrow manner;
Consisting of! y) Type-K field effect tofun V star. 2) The Schottky type can field effect transistor according to claim 1, wherein the substrate is a semi-insulating compound semiconductor. 6) The upper ε semi-insulating compound semiconductor is GILAJ.
J14 world effect tofunjista. 4) The Schottky type field effect transistor as claimed in claim 1, 2, or '#I5, wherein the active layer is an N-type beam 8. 5) A νgy) Q-type field effect transistor according to claim 1, 2, 3 or 44, wherein the gate electrode is made of molybdenum. 6) The side surface of the gate electrode is covered with a high-resistance material 1; V-eye type electric field effect)? Njista. 7] t! of the above gate electrode! Claim 1 characterized in that 1 is covered with an insulating material 6,
s2, 5th, 4th or 5th term 1-type field effect function νs! . 8) The operating layer directly above the gate sand is made thinner than the operating layer at other locations! ! Claim 1 characterized by I#
8 Section 1, Section 2, Section 3, Section 4, Section 5, Section 6 or Section 117e 7 Toki-type magnetic field effect [Funrasta.