JPS5846053B2 - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

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Publication number
JPS5846053B2
JPS5846053B2 JP12614377A JP12614377A JPS5846053B2 JP S5846053 B2 JPS5846053 B2 JP S5846053B2 JP 12614377 A JP12614377 A JP 12614377A JP 12614377 A JP12614377 A JP 12614377A JP S5846053 B2 JPS5846053 B2 JP S5846053B2
Authority
JP
Japan
Prior art keywords
electrode
semiconductor device
manufacturing
temperature
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP12614377A
Other languages
Japanese (ja)
Other versions
JPS5459079A (en
Inventor
隆志 大曾根
正紀 福本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12614377A priority Critical patent/JPS5846053B2/en
Publication of JPS5459079A publication Critical patent/JPS5459079A/en
Publication of JPS5846053B2 publication Critical patent/JPS5846053B2/en
Expired legal-status Critical Current

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Description

【発明の詳細な説明】 本発明は半導体装置およびその製造方法に関し。[Detailed description of the invention] The present invention relates to a semiconductor device and a method for manufacturing the same.

と(に浅い接合層を有する半導体基板への電極形成方法
に関するものであり、形成が従来と比べて容易で、かつ
形成後の熱処理によっても上記浅い接合層を破壊しない
ようなAl電極の形成を目的とするものである。
This invention relates to a method for forming an electrode on a semiconductor substrate having a shallow bonding layer, and it is possible to form an Al electrode that is easier to form than conventional methods and that does not destroy the shallow bonding layer even during post-formation heat treatment. This is the purpose.

近年、MO8型集積回路の高集積化による回路パターン
の微細化あるいはバイポーラトランジスターの高速化等
の要求から、ソース、ドレンやエミッタ拡散層の深さを
減少させ、浅くする必要性が生じる。
In recent years, due to the demand for finer circuit patterns due to higher integration of MO8 type integrated circuits and higher speed of bipolar transistors, it has become necessary to reduce the depth of source, drain, and emitter diffusion layers to make them shallower.

この様な浅い接合を持つ拡散層へ、従来から一般的に使
用されているAl電極を形成する方法では、Alが電極
形成後の合金化熱処理によって容易に拡散層に深く侵入
して接合を破壊する。
In the conventional method of forming an Al electrode on a diffusion layer with such a shallow junction, Al easily penetrates deeply into the diffusion layer during alloying heat treatment after forming the electrode and destroys the junction. do.

このため半導体基板−電極間のリーク・ショートを起こ
し、半導体装置の歩留り低下をまねき、この点での改善
が強く要求されている。
This causes leakage and short circuits between the semiconductor substrate and the electrodes, resulting in a decrease in the yield of semiconductor devices, and there is a strong demand for improvement in this respect.

そこで、浅い接合に対する電極形成方法の一つとしてS
iを含むA7を電極材料として使用する方法はよく知ら
れている。
Therefore, as one of the electrode formation methods for shallow junctions, S
The method of using A7 containing i as an electrode material is well known.

この電極を使えば、最初からAl中にSiを含むため、
電極形成後に熱処理を加えても、基板の半導体原子が電
極中に溶解する量及び基板中へ侵入するAl原子の量は
著しく少ない。
If you use this electrode, since Si is included in Al from the beginning,
Even if heat treatment is applied after electrode formation, the amount of semiconductor atoms in the substrate dissolved into the electrode and the amount of Al atoms penetrating into the substrate are extremely small.

従って、純粋7a’Alだけを使用した場合に起こる接
合破壊などは非常に少なくすることができる。
Therefore, bond breakdown that occurs when only pure 7a'Al is used can be greatly reduced.

しかし、Siを含むA7を半導体領域に形成するには蒸
着法が用いられるが、このとき蒸着源となる5i−A#
合金中のSi濃度を忠実に配線膜に再現性良く形成する
ことは技術的に高度なものであり極めて難しい。
However, in order to form A7 containing Si in a semiconductor region, a vapor deposition method is used, but at this time, 5i-A#, which serves as a vapor deposition source, is used.
It is technically sophisticated and extremely difficult to form a wiring film with good reproducibility while keeping the Si concentration in the alloy faithful.

それは、ある一定の温度におけるAlとSiの熱平衝蒸
気圧に大きい差があるからである。
This is because there is a large difference in thermal equilibrium vapor pressure between Al and Si at a certain temperature.

第1図は熱平衝蒸気圧と温度を示す図であるが、例えば
Siの融点付近1400’Cでは、AAの蒸気圧二Si
の蒸気圧−=500:1の比となり、かなり差があるこ
とがわかる。
FIG. 1 is a diagram showing the thermal equilibrium vapor pressure and temperature. For example, at 1400'C near the melting point of Si, the vapor pressure of AA is
It can be seen that the ratio is 500:1, and there is a considerable difference.

タングステンフィラメント等を用いる抵抗加熱蒸着法の
ような、蒸着源の温度が比較的低い蒸着法では、蒸着源
のSi濃度が数%であっても、この大きい蒸気圧の差の
ため、A7原子のみが速い速度で蒸着され、蒸着膜中に
Si原子がほとんど含まれない状態となる。
In evaporation methods where the temperature of the evaporation source is relatively low, such as resistance heating evaporation method using a tungsten filament, even if the Si concentration of the evaporation source is several percent, this large difference in vapor pressure causes only A7 atoms to is deposited at a high rate, and almost no Si atoms are contained in the deposited film.

さらに、気化して蒸着されなかったSiは蒸着源のフィ
ラメントに残留し、次の蒸着の際、蒸着源合金中のSi
濃度を増加させ、蒸着膜中のSi濃度再現性を悪くする
原因となる。
Furthermore, Si that is not vaporized remains in the filament of the deposition source, and during the next deposition, Si in the source alloy remains.
This increases the Si concentration and causes poor Si concentration reproducibility in the deposited film.

こうした事が起これはA7中のSi濃度が蒸着源のSi
濃度に比べて少ないために電極熱処理後、接合リークが
生じて歩留りを低下させたり、Al膜中のSi濃度変動
のため配線抵抗やコンタクト抵抗が変動し、工程管理上
好ましくない結果となる。
This happens because the Si concentration in A7 is the vapor deposition source.
Since the concentration is small compared to the Si concentration, junction leakage occurs after electrode heat treatment, reducing yield, and wiring resistance and contact resistance vary due to variations in Si concentration in the Al film, resulting in unfavorable results in terms of process control.

本発明はこのような現状に鑑みた検討の結果なされたも
ので上記欠点を改善する電極形成を行うものである。
The present invention was made as a result of studies in view of the current situation, and is intended to form an electrode that improves the above-mentioned drawbacks.

以下本発明の詳細な説明する。本発明の電極形成の特長
は電極材料としてゲルマニウム(Ge )を含むAlを
用いるものである。
The present invention will be explained in detail below. A feature of the electrode formation of the present invention is that Al containing germanium (Ge) is used as the electrode material.

GeはSiと同族の代表的な半導体であり、その結晶構
造、バンド構造等物性的に類似している点が多い。
Ge is a typical semiconductor of the same family as Si, and has many similarities in physical properties such as crystal structure and band structure.

特にAl−Ge 2元合金状態図はAdSi系と同じ共
晶反応型であり、Al−Ge固溶相を形成する温度も約
200℃から600℃近辺におよんでいる。
In particular, the Al-Ge binary alloy phase diagram is of the same eutectic reaction type as the AdSi system, and the temperature at which the Al-Ge solid solution phase is formed also ranges from about 200°C to around 600°C.

これはAl−8i系の固溶相と温度範囲が一致しており
、従って蒸着した配線用Al膜に最初からGeが含まれ
ている場合、後の電極熱処理の際に、Siを含むA7膜
と同じ効果を生じることが予想される。
The temperature range of this is the same as that of the solid solution phase of the Al-8i system. Therefore, if the vapor-deposited Al film for wiring contains Ge from the beginning, the A7 film containing Si will be removed during the subsequent electrode heat treatment. It is expected that the same effect will occur.

すなわち、A7膜中にSiと類似の性質を持つGeが最
初から含まれているのであるから、金属−半導体基板界
面から、半導体原子がA7膜中に拡散するのがおさえら
れる一方、A7も半導体基板中へ侵入しにくくなると考
えられる。
In other words, since Ge, which has properties similar to Si, is contained in the A7 film from the beginning, semiconductor atoms are prevented from diffusing into the A7 film from the metal-semiconductor substrate interface, while A7 is also a semiconductor. It is thought that it becomes difficult to penetrate into the board.

本発明者らはこのような着想にもとづき、実際に実験を
行なった結果、半導体基板へのA7侵入防止に効果があ
ることを確認した。
Based on this idea, the present inventors conducted an actual experiment and confirmed that the present invention is effective in preventing A7 from entering a semiconductor substrate.

まず、コンタクト面となる一導電形Si基板に17’程
度の深さに形成された反対導電形の半導体領域表面を、
NH4F:HF=10 : 1のエツチング液でエッチ
し、表面の薄い酸化膜を除去した後、(1〜10%)の
Geを含むA7合金を抵抗加熱法で蒸着した。
First, the surface of a semiconductor region of an opposite conductivity type formed to a depth of about 17' on a Si substrate of one conductivity type, which will be a contact surface, is
After etching with an etching solution of NH4F:HF=10:1 to remove a thin oxide film on the surface, an A7 alloy containing (1 to 10%) Ge was deposited by resistance heating.

真空度は1×10−6×〜1×10−5 Torrであ
った。
The degree of vacuum was 1×10 −6× to 1×10 −5 Torr.

その後、N2雰囲気、420℃でシンターをなない蒸着
したA1合金を除去しSi表面をSEM(電子顕微鏡)
で観察した。
After that, the A1 alloy deposited without sintering at 420°C in a N2 atmosphere was removed, and the Si surface was examined using an SEM (electron microscope).
I observed it.

第2図aは上記試料のSEM像であり、第2図すは従来
のAAを蒸着してシンク−した後のAl除去面である。
FIG. 2a is a SEM image of the sample, and FIG. 2a shows the surface from which Al has been removed after conventional AA has been deposited and sinked.

この図において1は表面のSiO2膜、2は拡散層表面
である。
In this figure, 1 is the SiO2 film on the surface, and 2 is the surface of the diffusion layer.

従来のAlでハアロイピット3が見られ、A7の拡散層
へのつき抜けが生じている可能性が極めて高い。
Haloy pits 3 are seen in conventional Al, and it is extremely likely that penetration into the A7 diffusion layer has occurred.

一方Geを含むAlを蒸着した試料では、表面に析出し
たGe4たけが見え、アロイピットはなく、A7の侵入
が防止されていることがわかる。
On the other hand, in the sample in which Al containing Ge was vapor-deposited, only Ge4 precipitated on the surface was visible, and there were no alloy pits, indicating that the intrusion of A7 was prevented.

ところでこのときシンク一温度をAA−Ge共晶温度4
24°C以上にすると、急速にAl−Si間の相互拡散
が起こり、アロイピットができることがわかった。
By the way, at this time, the sink temperature is AA-Ge eutectic temperature 4
It was found that when the temperature is 24°C or higher, interdiffusion between Al and Si occurs rapidly and alloy pits are formed.

従ってシンク一温度は共晶温度以下の424°C以下が
好ましい。
Therefore, the sink temperature is preferably 424° C. or lower, which is lower than the eutectic temperature.

このように、不発明者らはGeを含むAdを用いればA
7の侵入による接合破壊現象を減少させる効果があるこ
とを確認した。
In this way, the non-inventors found that if Ad containing Ge is used, A
It was confirmed that this method has the effect of reducing the phenomenon of bond breakdown due to the intrusion of No. 7.

ところでGeの融点は940℃、Siの融点は1.40
0℃である。
By the way, the melting point of Ge is 940°C, and the melting point of Si is 1.40°C.
It is 0°C.

従っである一定の温度の時、Geの蒸気圧はSiの蒸気
圧よりはるかに高いと考えられる。
Therefore, at a certain temperature, the vapor pressure of Ge is considered to be much higher than that of Si.

実際第1図に示すごとく、例えば1100℃の場合を比
較すると、A#:1X1O−Torr、Si:5X10
Torr、Ge:8X10−5Torrであり、
Alに対するGeの蒸気圧の比はSiの場合より非常に
小さいことがわかる。
In fact, as shown in Figure 1, for example, when comparing the case of 1100℃, A#: 1X1O-Torr, Si: 5X10
Torr, Ge: 8X10-5 Torr,
It can be seen that the vapor pressure ratio of Ge to Al is much smaller than that of Si.

不純物含有量wB%の蒸着源から蒸着した時、蒸着膜中
に入る不純物の含有量(FB%)を示す式で表わされる
ことが知られている。
It is known that when vapor deposition is performed from a vapor deposition source with an impurity content of wB%, it is expressed by a formula that indicates the content of impurities (FB%) that enters the deposited film.

ここで、AA tABはそれぞれAlおよび不純物の活
量、PA 。
Here, AA tAB are the activities of Al and impurities, PA , respectively.

PBはそれぞれAAおよび不純物の蒸気圧、MA。PB is the vapor pressure of AA and impurities, MA, respectively.

MBはそれぞれA7および不純物の分子量である。MB are the molecular weights of A7 and impurities, respectively.

この式かられかるように、Alに対する不純物蒸気圧の
比PB/PAによってFBは大きく左右される。
As can be seen from this equation, FB is greatly influenced by the ratio PB/PA of impurity vapor pressure to Al.

PB/PAが1に近い程蒸着源不純物濃度が、蒸着膜に
反映される。
The closer PB/PA is to 1, the more the deposition source impurity concentration is reflected in the deposited film.

従って、Geを含むA7を蒸着する方が、蒸着膜中の不
純物濃度は蒸着源不純物濃度に近いものとなるのである
Therefore, when A7 containing Ge is deposited, the impurity concentration in the deposited film becomes closer to the impurity concentration of the deposition source.

以上の様に、Geを含むAlを電極材料として使えば、
Siを含むA7の場合より蒸着膜中の不鈍物濃度が蒸着
源不純物濃度に近くなるため、抵抗加熱蒸着法でも、蒸
着源不純物濃度に近いGeを含むAl電極が形成できる
As mentioned above, if Al containing Ge is used as an electrode material,
Since the impurity concentration in the deposited film is closer to the deposition source impurity concentration than in the case of A7 containing Si, it is possible to form an Al electrode containing Ge close to the deposition source impurity concentration even by the resistance heating evaporation method.

従って、蒸着源のフィラメントに蒸着されずに残留する
上記不純物量も減少させることができ、繰返しての蒸着
が容易となる。
Therefore, the amount of the impurities remaining on the filament of the deposition source without being deposited can be reduced, and repeated deposition becomes easy.

さらにAl中のGeは、電極熱処理に対してSiと同様
な効果を示し拡散層へのAA侵入による接合破壊を防ぎ
、接合リークによる集積回路歩留り低下をおさえること
ができる。
Furthermore, Ge in Al has the same effect as Si on electrode heat treatment, prevents junction breakdown due to AA intrusion into the diffusion layer, and can suppress reduction in integrated circuit yield due to junction leakage.

尚、本発明の説明にはGeのみを含むAl電極の形成法
について述べたが、Geを主成分としてSiを混入して
もよい。
Although the present invention has been described with respect to a method of forming an Al electrode containing only Ge, Si may be mixed with Ge as the main component.

AA中に少量のSiが混入すると、従来の方法からもわ
かるようにシンク一温度を424℃以上にしてもAnの
8i基板中への侵入か起こり難くなる。
If a small amount of Si is mixed into AA, it becomes difficult for An to penetrate into the 8i substrate even if the sink temperature is set to 424° C. or higher, as can be seen from the conventional method.

従ってA7中にGeを主成物としSiを混入すると、G
eのみの場合より高温(424℃以上)でシンターでき
るため、Alによる接合破壊防止たけでなく低抵抗オー
ミックコンタクト形成等に効果を発揮するものである。
Therefore, if Ge is the main component and Si is mixed into A7, G
Since it can be sintered at a higher temperature (424° C. or higher) than when only e is used, it is effective not only in preventing junction breakdown due to Al but also in forming low resistance ohmic contacts.

以上のように本発明は、不純物としてGeを含むA7電
極を用いることにより、シリコン層に形成された深さの
浅い反対導電影領域の電極形成を確実かつ容易に行うこ
とができ、高密度半導体集積回路の製造に大きく寄与す
るものである。
As described above, by using the A7 electrode containing Ge as an impurity, the present invention can reliably and easily form an electrode in a shallow opposite conductive shadow region formed in a silicon layer, and This greatly contributes to the production of integrated circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はAd 、Si 、Geの温度とそれぞれの熱平
衡蒸気圧の関係を示す図、第2図aはGeを含むAA合
金電極形成後シンク−して電極を除去した半導体基板表
面の5000倍のSEM像(電子顕微鏡写真)、第2図
すは従来のAl電極形底抜、シンターしてA7を除去し
た基板表面の同5000倍のSEM像(電子顕微鏡写真
)である。 1・・・・・・S t 02膜、2・・・・・・拡散性
、4・・・・・・Ge。
Figure 1 shows the relationship between temperature and thermal equilibrium vapor pressure of Ad, Si, and Ge, and Figure 2a is 5,000 times the surface of the semiconductor substrate from which the electrode was removed by sinking after forming an AA alloy electrode containing Ge. Figure 2 is an SEM image (electron micrograph) of the surface of a conventional substrate with an Al electrode type bottom cut out and sintered to remove A7. 1...S t 02 film, 2... Diffusivity, 4... Ge.

Claims (1)

【特許請求の範囲】 1 シリコン層にゲルマニウムを含んだアルミニウム電
極を形成したことを特徴とする半導体装置。 2 アルミニウム電極が、ゲルマニウムを主成分として
シリコンを含むことを特徴とする特許請求の範囲第1項
に記載の半導体装置。 3 シリコン層にゲルマニウムを含んだアルミニウムを
蒸着形成し、熱処理して上記シリコン層の電極を形成す
ることを特徴とする半導体装置の製造方法。 4 蒸着形成ののち、共晶温度以下の温度で熱処理する
ことを特徴とする特許請求の範囲第3項に記載の半導体
装置の製造方法。 5 アルミニウムがゲルマニウムを主成分としてシリコ
ンを含んだことを特徴とする特許請求の範囲第3項に記
載の半導体装置の製造方法。
[Scope of Claims] 1. A semiconductor device characterized in that an aluminum electrode containing germanium is formed in a silicon layer. 2. The semiconductor device according to claim 1, wherein the aluminum electrode contains silicon as a main component and germanium as a main component. 3. A method of manufacturing a semiconductor device, comprising depositing aluminum containing germanium on a silicon layer and heat-treating the silicon layer to form an electrode of the silicon layer. 4. The method for manufacturing a semiconductor device according to claim 3, wherein after the vapor deposition, heat treatment is performed at a temperature below the eutectic temperature. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the aluminum contains germanium as a main component and silicon.
JP12614377A 1977-10-19 1977-10-19 Semiconductor device and its manufacturing method Expired JPS5846053B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12614377A JPS5846053B2 (en) 1977-10-19 1977-10-19 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12614377A JPS5846053B2 (en) 1977-10-19 1977-10-19 Semiconductor device and its manufacturing method

Publications (2)

Publication Number Publication Date
JPS5459079A JPS5459079A (en) 1979-05-12
JPS5846053B2 true JPS5846053B2 (en) 1983-10-14

Family

ID=14927731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12614377A Expired JPS5846053B2 (en) 1977-10-19 1977-10-19 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JPS5846053B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5288456A (en) * 1993-02-23 1994-02-22 International Business Machines Corporation Compound with room temperature electrical resistivity comparable to that of elemental copper

Also Published As

Publication number Publication date
JPS5459079A (en) 1979-05-12

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