JPS5844559A - Display system of electronic device - Google Patents

Abstract

PURPOSE:To ensure the extremely natural reading of the display contents larger than the display capacity, by having a running display of the data to be fed and furthermore varying the indicated contents in case a halt state arises in the course of a calculation. CONSTITUTION:It is supposed that a counter is previously reset at 0. Then the code of ''DE'', for example, is stored in a character memory to display ''DE''. Then the contents of the character memory is shifted left by an extent equivalent to one digit of display. Then ''DE'' is displayed after the end of display of ''DE'', and then the ''DATA'' is displayed. Then the code of A is stored in the character memory in the first halt state, and then the data A is displayed. Then ''Feed data A.'' is displayed repetitively. Then the counter value is set at 2 in the second halt state, and the code of B is stored in the character memory to display ''Feed data B.'' In the same way, ''Feed data C.'' and ''Feed data D.'' are displayed in the 3rd and 4th halt states respectively.

Description

[Detailed description of the invention]

The present invention relates to a display system in electronic equipment such as an electronic calculator, and more particularly to a new display system for controlling and operating the display of a computer or the like. Conventionally, in the display system of an electronic calculator, if it is desired to display more digits than the number of digits of the display, the data to be displayed must be divided and switched two or more times for display. However, such a switching method has a drawback that the relationship (connection) between the previously displayed display content and the currently displayed display content is not clear, leading to misreading. The present invention is to overcome the aforementioned difficulties. The purpose of the present invention is to shift the display content of a display body capable of displaying characters such as numbers, letters, symbols, etc. at regular intervals (hereinafter referred to as running display), thereby exceeding the display capacity that can be displayed on the display body. The purpose of the present invention is to provide a display method for electronic calculators, etc., which can display displayed information, and thereby overcome the above-mentioned conventional difficulties by continuously moving the display contents [7, and in addition, it is necessary to switch between one display and the other. There is no
It is an object of the present invention to provide a display method for electronic calculators, etc. that can be read very naturally by an operator. One feature of the present invention is that the display contents are cycled so that after a certain display content is displayed running and disappears from the edge of the display section, the beginning of the same display content is displayed again. To obtain a display system in which the beginning of the same display content is not displayed until the content is shifted and completely disappears from the edge of a display part, and the display divisions are clear and there is no misreading. Another feature is that by providing a display method that can distinguish between normal display (so-called static display) and running display (dynamic display) depending on the type of display content, for example, data such as calculation results can be A normal (stationary) display is performed, and instruction displays such as calculation procedures are differentiated by shifting them at regular intervals, and even if the display 5 has the same content, the droop of the display can be differentiated depending on the display state. The goal is to be able to do this.・This method is particularly effective when used in scientific calculators, etc. Another feature is that the display content can be changed to the level of one loaded car, and the computer can be displayed in the Hart state (
If a so-called state in which the calculation is temporarily stopped until data is input at a step where data is input from an external device during execution of the program, the contents of the character indicating the next data to be input are displayed [7, Another object of the present invention is to provide a display system for a computer, etc., which has various functions that allow character contents to be varied depending on the internal state of the computer and to display calculation results for a certain period of time immediately before the display state. Further objects and advantages of the present invention will become apparent from the following description and the accompanying drawings. FIG. 1 is an external view showing an embodiment of a program computer equipped with the display system of the present invention, and FIG. 2 is a state diagram showing an example of the display state of the computer. In Fig. 1, 1 indicates the display section and 2 indicates the key manual section [7,
FIGS. 2(a) to 2(i) will be described with reference to 17 as an example of a case in which data to be input next is specified when a scientific calculator or the like enters the Hart state during calculation. Here, (a) is a normal display, rb) to (g) are display states at the time of display based on the display method of the present invention,
(b) is the display state of the first character of the instruction for the next data to be input, and after a certain period of time (for example, 0.5 seconds) it will be in the state of (c), and after the next 0.5 seconds, it will be in the state of (d). Become. In this way, the display contents shift at regular intervals, (b)-・fc)-
'(d)...(e)→(f)→...(g)-=
(h) → (i), and after all the displays disappear, the state changes to (b), and thereafter the display is repeated in the same way. FIG. 3 is a block diagram of an embodiment of a computer equipped with the display system of the present invention. In the figure, 3 is the key human power device, 4
is a central processing unit r (Cent-ral-Pr), which will be described later.
cessor-Unit) Hereinafter referred to as CPU. ” is a device that decodes and executes instructions. 5 is register S
A, galactage generator (CRG) decodes the output signal from SX; 6 indicates a 5×7 8-digit dot matrix type display; 7 indicates a digit selection signal; and 8 indicates a segment signal. FIG. 4 is a logic circuit diagram of an embodiment of a CPU device of a computer that executes the display method of the present invention;
Includes 4D diagram. FIG. 5 is a diagram illustrating a circuit equivalent to the CPU device of FIG. 4. The specific logic circuit configuration of the CPU will be described below. (Circuit configuration of CPU) The RAM is a random access memory chip. Input/output is performed in units of 4 bits, and desired digit content can be input/output by specifying a decid address and a file address. BL is the memory RAM digit address counter, DC. is the memory RAM digit address decoder, BM
is the memory RAM file address counter, DC2
is the memory RAM file address decoder, A D
l is an adder, which operates as a subtracter when the control command 0 is given, and as an adder when 0 is not given. A
D2 is an adder, G1 is an adder/subtractor AD, and is a gate for giving either the numerical value l or the operand IA to one input.When the control command ■ is given, it gives I, and when it is [phase], it gives ■. output. G2 is the input gate of the memory leap order address counter BL, and when it is [phase], it is the adder/subtractor A.
The output of D1 is the operand ■I when the time is ■, and the operand ■8 when it is 00. G3 is adder/subtractor A D 2
This is a gate for supplying either the numerical value l or the operand I to one input of the circuit. G4 is the input gate of memory file address BM,
When ■, the output of adder AD2 is used, and the r beat is the operand IA.
, when ■, the contents of accumulator ACC are output. G5 is the memo 'J-RAM file) V selection gate, DC3 is the decoding gate of operand IA, operand I
Decipher A and send the specified signal to gate G (desired memory via)
5. G6 is a memo! ] - RAM input gate, when control command ■ is given, operand decoder Dc
Manually write a binary number 1 to the desired bit of the memory specified by 3, and when it is ■, set the desired bit of the memory specified by DC3.
It has a built-in circuit that inputs a binary number 0 to the node, and also outputs the contents of the accumulator ACC at ■. ROM is lead
Only memory, PL is program counter,
Specify the desired input 7 of the read-only memory ROM. DC4ke IJ - Only Memory RO
M's step accelerator decoder, G7 is the read-only memory ROM output gate, and when the judge flip-flop (F/F) J is set, the ROM
The transmission of the output to the instruction decoder DC5 is cut off. DC5 is an instruction decoder,
It decodes the instruction code from the ROM, and the instruction code in the ROM is the operation code part I. and operand part IA. IB, the operation code is decoded, and one of control commands (1) to groan is generated in accordance with the operation code. It also has a built-in circuit that determines that the opcode is accompanied by an operand, and outputs the operand IA or IB as is at that time. AD3 is an adder that adds the value 1 to the contents of the program counter PL to count up. G8 is the input gate of the program counter PL, [phase]
When , the operand 4 is output, and when it is [phase], the contents of the program stack register SP are transmitted. The output of the adder AD3 is not transmitted during the processing of [phase], season, and the processing of [stock] for G39. Other than [phase], [phase], and 轡, the AD3 output is transmitted and 1 is automatically added to the contents of the program counter PL. FC is stack 5,
G9 is the input gate of flag F/FFC, when it is @, it is a binary number ■, and when it is 0, it is a binary number 0, respectively.
This is something that cannot be entered into C. GIO is a key signal generation gate, and when the flag F/FFc is in the reset state (0), the desired output of the memory digit address decoder DC is output as is, and when the flag //FFC is set state 1, it is output as is. D.C. Regardless of the output, (1) has a built-in circuit that sets the outputs of 1 to In all to 1 at the same time. ACC is an accumulator made up of 4 bits, and X is a temporary made up of 4 bits.
(temporary storage) register, G11 is the input gate of temporary register
When it is [phase], the contents of the stack register SX are transmitted. AD4 is an adder, and accumulator A
It is used to perform binary addition of the contents of the CC and other data. During binary addition, if a carry occurs in the addition of the fourth bit, the c4 output is set to 1. C is carry '/1;, G+2
is the carry input gate, and when the control command ■ occurs,
If the fourth bit carry C4 is 1, carry F/
It has a built-in circuit that inputs 1 to /FC and inputs 0 to C if C4 is 0. This is for inputting 1 to C when it is [phase], and CKO when it is [phase]. G13 is a carry C input gate for performing binary addition including carry in adder AD4, and when in [phase], carry F/FC is input.
The output of is transmitted to adder AD4. GI4 is the input gate of adder AD4, and when it is [phase], please note! The output of l-RAM is set to the operand IA when it is [phase].
Communicate. F is an output buffer register consisting of 4 bits, and GI5 is an input gate of the output buffer register F, which transmits the contents of the accumulator ACC and inputs it to F at the time of [phase]. SD is an output decoder for decoding the contents of the output buffer register F and converting it into display segment signals SS1 to SSn. W is an output buffer register, and SHC is for shifting all bit contents of the output buffer register W by 1 bit to the right at the same time, and operates when qyu or [phase] occurs. This is a shift circuit for the output buffer register W. G16 is the input gate of the output buffer register W, which inputs 1 to the first bit of W when it is [phase], and inputs 0 to the first bit of W when it is [phase].
It is for inputting 1 or 0 to the first bit of W, and immediately before inputting 1 or 0 to the first bit of W, the output buffer shift circuit 5I
(Assume that C operates and is input after shifting. N, is the output control flag '/p
, G+ytj: Output con) o-/l/7lag F/
At the input gate of FNP, input 1 when it is [present], and input 0 when it is [phase]. G11l is buffer register W
At the output control gate of , only when the flag F//FN is set (1), the output of each bit of W,
This is to output power all at once. j' is the sheet switch, v1 to Iv are the inverter circuits, 019 is the input gate of the judge F/FJ, and the input KN is
, to transmit the status of , to J. However, since it is via inverter IV, when KN = 0, J =
It becomes 1. G20 is the input gate of judge F/FJ,
At [phase], the state of input KN2 is transmitted to J. Ta! However, since it is passed through inverter IV2, J=1 when KN2=0. G21 is the input gate of judge F/FJ, and is used to transmit the state of input K F 1 to J at [phase]. -fi-'i through inverter Iv3, so when KF+=O, KJ=1. ! :Become. G2□ is the input gate of Ja Shiji F4J, and when it is [phase], the input KF
This is for transmitting the status of 2 to J. Since it is passed through the inverter IV4, J=1 at KF2. G
23 is the input gate of judge F/FJ, and is for transmitting the state of input AK to J at the time of ・Yu. When AK=1, J=1. G24 is the input gate of judge /i-J, which is used to transmit the state of input TAB to J at the time of ■. When TAB=1, J=1. G25 is Ja-
This is a gate for setting F di/i-J, and is for inputting 1 to J when ■. vl is a comparison circuit that compares the contents of the memory digit address counter BL with predetermined data and generates an output of 1 if they match.
The circuit operates when [phase] or [present] is generated. The data to be compared is output from G26. G2
6 is a comparison value input gate to the comparison circuit v1, and the comparison value n,
corresponds to a specific address value on the high side that is often used for controlling the memory RAM. When it is [phase], nl is outputted to use as a comparison value, and when it is [present], n2 is outputted to be used as a comparison value. G2□ is the input gate of J7J F/FJ, and when the content of carry F/1l-C is 1 at the 6th time, 1 is input to J. DCs is a decoder for operand IA, and operand ■4
Decipher and take notes! It is used to judge whether the content of a desired bit in J-RAM is 1 or not. G2g is a gate that transmits the bit contents designated by the operand decoder DC6 of the memory RAM to the judge 4, and operates in [phase]. R
When the designated bit of AM is 1, J=1. v2
is a comparator circuit that judges whether the contents of accumulator AC'C' and the contents of operand I are equal, and generates an output of 1 when they are equal. ■It works when. A comparator circuit v3 judges whether the contents of the memory digit address counter BL and the contents of the operand IA are equal, and generates an output 1 when they are equal. Operates at [phase]. A comparison circuit v4 judges whether the contents of the accumulator ACC and the contents of the memory RAM are equal, and generates an output l when they are equal. G29 is a (f) transmission gate to judge F//FJ of addition fourth bit carrier C4, which transmits C1 to /, J in [phase]. J at C4
=1. FA is flag fritz flip lop, G31
is the input gate of the flag/FFA, which outputs 1 at this [phase] and 0 at 00. G32 is the input gate of judge l/FJ, and when flag F/, FA is 1, F/FJ
Add a cent (+) to F8 is a flag gate, and G33 is an input gate for flag l/FEB, which outputs 1 when it is [phase] and outputs 0 when it is [phase]. G34 is Judge F/F-
The input gate of J transmits the contents of flag/FEB to '/FJ. Operates when in [phase]. G35 is an input gate of judge/FJ, which transmits the contents of input B and operates according to [phase]. When B=1, J=1. G36 is an input gate of the accumulator ACC, which transmits the output of the adder AD4 when in [phase], and inverts and transmits the contents of the accumulator ACC by inverters IV and 5 when in [phase]. When it comes to [phase], take notes! J
-Transmit the contents of RAM, and when it is [phase], the operand IA
Communicate the content of When it is [phase], the contents of 4 bits 1 to 4 are transmitted to the input. At [phase], the contents of stack register SA are transmitted. IV5ij: Inverter circuit, SA is a stack register whose output is led out of the system. SX is a stack register whose output is led out of the system. G37 is an input gate of the stack register SA, which transmits the contents of the accumulator ACC in [phase]. 638 is the input gate of the stack register SX, which transmits the contents of the temporary register This is to introduce into the program stack register the contents of which are added by fv in adder AD3. An example of a control command generated based on an instruction code is shown in the table below. In the table, A: instruction code, B: instruction name, C: content, and D: CPU control command. Table 1 (C) Description I 5KIP Do not execute the next program step instruction, increment only the narogram counter PL, and essentially skip it.AD Add the contents of the accumulator ACC and the contents of the memory RAM in binary, and add the addition result to the accumulator ACC. ADC Accumulator ACC, memory *A+v. Kiya!J -F/p Add the contents of C in binary and input the addition result to accumulator ACC. 4 ADC5K Accumulator ACC, memory RAM. Kiya!J Add the contents of -F/11-C in binary and input the addition result to the accumulator ACC. If the fourth bit carry C4 occurs as a result of this addition, skip the next program step. 5 ADl Contents of the accumulator ACC and binary addition of operand Ij] 7. Input the addition result to accumulator ACC, and generate the fourth bit carry C4 with this addition result, thus skipping the next program step. DC Operand IA is 1010 (decimal number 10 ), A
Similar to the DI instruction, by adding the contents of the accumulator ACC and this operand IA in binary, the contents of the accumulator ACC are essentially added with a decimal number 10.
Input the result to ACC. 5C Carry F/FC Set C. (Input 1 to C.) 8 RC'□ Carry F/FC Reset C. (Input 0 to C.) 5M Deciphers the contents of operand IA and stores the desired bit in the memory specified by the operand. (Input 1.) 10 RM Decodes the contents of operand ■4 and resets the desired bit in the memory specified by the operand. (Input 0.) II COMA Inverts the contents of each bit of accumulator ACC and sets it to 15.
Take the complement of and input it to accumulator ACC. 12 Lr) 1 Introduce operand IA' into accumulator ACC. 3 L Memo! The contents of j-RAM are introduced into the accumulator ACC, and operand 4 is input into the file address counter BM. 4LI Loads the contents of the memory RAM into the accumulator ACC and inputs the operand IA into the memory file address counter BM. Furthermore, the memory digit address counter BL is increased. If the content of BL is equal to the predetermined value n1, the next program step is skipped. +5LD Memo! The contents of J-RAM are introduced into the accumulator ACC, and the operand ① is input into the memory file address counter BM. Furthermore, the memory digit address counter BL is decreased. However, when the content of BL is equal to the predetermined value n2, the next program step is skipped. 6 X Exchanges the contents of the memory RAM and the contents of the accumulator ACC, and inputs the operand It-memory file address counter A to BM. 7XI Exchanges the contents of the memory RAM and the contents of the accumulator ACC, and inputs the operan)-I to the memory file address counter BM. Furthermore, the memory digit address counter BL is incremented. However, when the contents of BL are equal to the predetermined value n1, the next program step is skipped. 18 Statement D Exchanges the contents of the memory RAM and the contents of the accumulator ACC, and inputs the operand It-memory file address counter BM. Furthermore, the memory digit address counter BL is decreased. However, when the content of BL is equal to the predetermined value n2, the next program step knob is skipped. 19 LBLI Operand ■ inputs memory digit address counter BLK. 0LB Operand IA to memory file address counter B
At the same time, the operand 8 is input to the memory digit address counter BL. 21 ABLI Add the contents of memory digit address counter BL and operand IA'f binary 17, and put the addition result in BL. However, (7) When the content of BL is equal to the predetermined value n1, the next program is skipped. 22 ABMI Adds the content of memory file address counter BM and operand IA in binary, and puts the ~ addition result into BM. 8 T Input the operand into the program counter PL. 24 5KC If the carry F/FC is 1, skip the next program step. 25 5KM Decode the contents of the operand and store the memory specified by the operand. If the desired focus is 1, skip the next program step. 26 5KBI Methyly digit address number BL Compares the contents of L with operand ■4, and if they are equal, skips the next program step. 27 8KAI Accumulator Compare the contents of ACC and operand IA, and if they are equal, skip the next program step. 28 5KAM Compare the contents of accumulator ACC with the contents of memory RAM 1-1' If they are equal, skip the next program step. 29 5KN. K N , When the input is 0, skip the next program step. 3Q 5KN2 K N 2 When the manual power is 0, skip the next program step. 81 5KF1 KF, When the input is 0, skip the next program step. 32 5KF2 When KF2 manual power is 0, skip the next program step. 38 5KAK When AK large input is 1, skip the next program step. 84 5KTAB When TAB input is 1, skip the next program step. Skip the next program step. 35 5KFA Flag E/FF When F 4 is 1, skip the next program step. 36 5KFB Flag F/FF When B is 1, skip the next program step. 7WIS 8WIR Shifts the contents of the output buffer register W to the right by 1 bit and inputs 1 to the first bit (most significant bit).8WIR Shifts the contents of the output buffer register W to the right by 1 bit and inputs 1 to the first bit (most significant bit ). 89 NFS Buffer register W output controller I Set F/PNP. (Input 1.) 40 NPR Reset buffer register W output controller IV F/FN. (Input 0 ) 41 ATF Outputs the contents of accumulator ACC.
Transfer to. 42 LXA The contents of accumulator ACC are transferred to temporary register
to be introduced. 48 XAX Contents of accumulator ACC and temporary register X
exchange the contents of 44 SFA Flag F, /1l-Sect FA. (Input l.) 45 RFA Flag F/F F BIr: Reset. (Input 0.) 46 5FB Set flag F4FB. (Input 1.) 47 RFB Reset flag F/, FB. (Input 0.) 48 5FC Set input test flag F/'FFc. (1
Enter. ) 49 RFC Reset input test flag F/FFc. (0
Enter. ) 50 5KB When input β is 1, skip the next program step. 51 KTA Input the contents of 1 to 4 into the accumulator ACC. 52 5TPO Transfers the contents of accumulator ACC to stack register SA and stores the contents of temporary register
Introduce it to X. 53 EXPO The contents of the accumulator ACC and the contents of the stack register SA are exchanged, and the contents of the tempo register X and the contents of the stack register SX are exchanged. 54 TML Transfers the contents of program counter PL plus 1 to program stack register SP. Furthermore, an operand IA is introduced into the program counter P. 5RIT Transfers the contents of the program stack register SP to the program counter P. Second, Table 2 shows the relationship between the opcodes and operands stored in the ROM (read only memory) in the CPU device. Table 2■. AD→0OOIOIIOQO ■. COMA→0001011+11 ↓ to DC. However, ■o=opcode■i■B: Oberando, for example, read-only memo-less ROM
For example, if the output of 10 bits is 10 bits, the instruction AD or COMA (see Table 1) will be output by the instruction decoder DC5, and the 10 bit code will be 0001011000 or 0001011111, respectively.
Deciphering that 1. A control command [phase], @ or [phase] is generated based on the judgment. On the other hand, 5KBI is determined by the fact that the upper 6 bits are 000110, and at this time, the lower 4 bits (0010) are treated as operand IA. Further L
B is determined by the fact that the upper 2 bits are 01, and at this time, the 3rd to 8th bits 001010 are treated as operand IA, and the 9th... 10th bit 11 is operand IB
treated as. An operand is a constituent part of an instruction word, and is a part that indicates data, an address where the next instruction is stored, etc., and can be called an address part of the instruction. Next, an example of the main processing operations of the above-mentioned CPU device (hereinafter referred to as a processing list) will be explained. (Processing list) (1) Note down the same number N! Insert it into the desired area of J-RAM. (NNN→X) (2) Introduce a plurality of different predetermined numerical values into a desired area of the memory. (NI+ N2+ N3...→X
)(3) Transfer the contents of the desired area of the memory to another desired area of the memory. (X-+Y) (4) Exchange the contents of a desired area of memory with the contents of another desired area of memory. (X-Y) (5) Predetermined numerical value N(a) f in the desired area of memory
The contents of other areas are added in decimal to the contents of the desired area of the i memory. (X±Y) '' (7) Shift the contents of the memory in the desired area by 1 digit. (X right, X left) (8) Set or reset the 1-bit conditioner #F/F in the desired area of the memory (Fset. Freset) (9) Judge the contents of the 1-bit conditional F/F in the desired area of memory, and change the next program address based on the judgment result. 0(i) The judge 12 determines whether the digit content is a predetermined value, and the judge 11 determines whether the contents of the plurality of digits in the desired area of the memory are all equal to the predetermined value. Change the program step based on the judgment result. a) Judge whether the contents of the desired area of memory are smaller than a predetermined value [7. Change the next program step based on the judgment result. Q:I Desired area of memory Judges whether the content of is larger than a predetermined value, and changes the next program step based on the judgment result. 0 → Displays the content of the desired area of memory. Qf9 Determines the type of suppressed key switch Next, a specific example of executing the above processes (1) to αυ based on the instruction code will be explained below according to the process list. (Specific example of process list) (Type I) Pl...・Specify the first digit to be processed in the memory using the file address mA and the decend address nE. P2... Introduce the numerical value N to ACC. P3... Exchange the contents of memory and ACC. Inserts the number N into the specified area of memory by .The file address in memory remains the same, so specify mA I7, and the digit address is down to determine the next digit to be introduced.Last digit to be introduced. By predetermining the value of nA as n2, the numerical value N is introduced into the entire desired area i, and when completed, BL=n
2, so skip the next P-4 and type
Finish processing 1. Pc... Specify program address k P 2 and select B
Repeat the LDI and XD processes until L=V. ■ PI: Specify the digit to be processed in the memory using file address mB and digit address nc. P2... Introduce the numerical value N to ACC. P3: Introduce the number N into the specified area of memory by exchanging the contents of memory and ACC. In this way, the Type 2 processing ends. The operand part of Xo is necessary for the subsequent processing and is not related to this processing. ■ Pl...--First file address mc to be processed in memory and digit address n. Specify with. P2... Introduce the numerical value N to ACC. P3...Introduce the number N into the specified area of memory by exchanging the contents of memory and ACC. The memory file address will not change, so specify me, and the digit address will be the next digit to be introduced.
Will be down to decide. P4...When checking whether the digit processed in P3 was the final digit nB, when it was n8,
Since the digit address has decreased to nA, when the operand part of the SKI instruction is set to nA, the number N is introduced to the final digit and the process proceeds to P4, the condition is not satisfied and the next address P5 is Skip and exit rypea. If the conditions are not satisfied, proceed to P5. P5... Set the program address to p2icm, and execute BL
Repeat the processing of P2 to P4 until = nA. ...→X) (Type) 4-digit numerical value N 4 N s N 2 N
An example of introducing + into memory is shown. (The same applies to the introduction of arbitrary digits) Pl...The first digit F to be processed in the memory is set to the file address mA and the digit address n.
Specify with H. Introduce a first constant N to Pl...ACC. P3...Introduce the numerical value N1 into the designated area of memory by exchanging the contents of memory and ACC. Since the memory file address does not change, mA is specified, and the digit address is updated to determine the next digit to be introduced. P4...Introduce a second constant N2 to ACC. Since the memory is designated as the second digit in the processing of P5...P3, the second constant N2 is introduced into the second digit of the memory by exchanging the contents of the memory and ACC. P6 to P, ... Process in the same way as above (TYI) e2
) When introducing any numerical value from 0 to 15 into a pre-filled register. Pi...Introduce a numerical value N to ACC. Pl...Introduces the numerical value N contained in ACC into register X. □ ■ PI-°°Specify the file address of the first memory to be heat-treated in mA12, and specify the first digit address to be processed in nH. Pl...The content of the desired digit in the first memory is A.
In addition to introducing it into the CC, in preparation for the transfer process at P3, the file address of the second memory of the transfer destination is specified in mB. P3...The contents of the first memory introduced into the ACC are P3.
The contents of the same digit in the second memory specified by l are exchanged to essentially transfer the contents of the first memory to the second memory. In order to repeat this process simultaneously, the original file address of the first memory is specified in mA. By predetermining the value of the final digit nA to be transferred as nl, BL=nl when all the contents of the first memory have been transferred to the second memory, so the next P4 is skipped and Typ.
e Finish the process of 1. BL=V, (last digit)
Upgrade the digit address one by one until 1. TeP
, the file address returned to Pl is set to mA, and the first memory is specified. Pc... is specified in the Glodarum address stealing step P2, and the transfer process is performed every 17.1 digits by repeating the commands P1 and P3 until BL=nl. Pl: Specify the memory area to be processed using file address mA and digit address n-c. P2...Contents of the memory area specified by PI-1A
cc, and specify the file address of the transfer destination memory with m in preparation for transfer processing in P4. P3: Specify the digit address of the transfer destination memory. The transfer destination memory area is specified in the processes P2 and P3. Pc...The contents of ACC are exchanged with the memory area designated by P2*P3, and are essentially transferred. The operands of X are directly related to this process.1. do not have. (Type 3) Pl: Specifies the memory area to be processed using file address mA and digit address nc. P2... AC the contents of the memory area specified by Pl.
Introduce it to C. P3: The contents of the memory introduced into ACC are introduced into register X, and desired Type 8 transfer processing is executed. Pl... File at the first memory to be processed,
The address to be processed is specified by mA, and the first digit address to be processed is specified by nE. P2...The content of the desired digit in the first memory is A.
In addition to introducing it into the CC, the file address of the second memory is specified in mB in preparation for the exchange process with the second memory in step 11''P3.P3...The first memory in the ACC Exchange the contents of the desired digit in the memory with the contents of the same digit in the second memory specified by P2, and introduce the contents of the second memory transferred to AC'C in this process into the first memory. In order to do this, specify the file address of the first memory in mA.P4...The contents of the second memory introduced in the ACC,
The contents of the first memory of the same digit are exchanged, and the second
Transfer the contents of the memory to the first memory. P2~P4
In this process, contents are exchanged between desired digits in the memory. The designation of the first memory is continued by designating the file address mA, the digit address is increased, the next digit address is designated, and the exchange is performed for each digit in sequence. The final digit n to be exchanged
By predetermining the value of A as nl, B1=nl when the contents of the first memory and the second memory have been exchanged over all digits, so the next P5 is skipped, Type 1 processing ends. P5...Specify the program address to P2, B. Repeat commands P2 to P4 until = n1 1-11
The exchange process proceeds digit by digit.
Pl...Specify the file address of the first memory to be processed in mA, and specify the decind address to be processed in n.
Specify with. P2...The contents of the desired digit 7 of the first memory are A.
At the same time as introducing it into the CC, specifying the file address m of the second memory, and preparing for content conversion. P3... Digit address n of the second memory of the transfer destination. 12, and determine the memory address of the replacement destination. P4...^Convert the contents of the first memory stored in C6C and the contents of the second i memory. At this time, A specifies the file address of the first memory again with m8 in order to transfer the contents of the second memory to the first memory to be transferred to the CC. P5: Specify the digit address nc of the first memory and determine the first memory address of the transfer destination. P6... Executes the exchange of the contents of the second memory contained in the ACC and the contents of the first memory δ (Type 3
) ■ P, ... Specify the file address of the first memory to be processed in mA, and the digit address to be processed in n.
Specify with. P2: Introduces the contents of the first memory into the ACC, and specifies the exchange destination using the file address mc of the second memory. P3...Exchanges the contents of the first memory of ACC and the contents of the second memory designated by %P2, and introduces the contents of the first memory into the second memory. In preparation for processing in P4, the first memory is designated again with the file address mB. P4...by exchanging the contents of the second memory introduced into the ACC with the contents of the first memory. The contents of the first memory and the second memory are exchanged. ■ Pl... File at address the memory area to be processed. P2...Contents of memory specified by PI'zAc
c. The file address mB is maintained for exchange with the contents of register X. P3... Exchange the contents of the memory in ACC with the contents of register X (7. Transfer the contents of memory to register X. P4... Exchange the contents of register X in ACC with memory By doing this, the contents of register P2...Introduce the contents of the memory specified by Pl into ACC.Specify mB as the memory file address in order to return to the same memory later.b...Numeric value to be added by operand Specify N 1-1A
Add the contents of the memory introduced in the CC and the numerical value N12,
The results will be requested from ACC. P4...Specify the sum found in ACC with P2

[7] Exchange the contents of the original memory and execute Type 1. (TYpe 2)X +-N→X ■ P,...Exchange the contents of register X and ACC. P2... Specify the numerical value N to be added with the operand 1-1
The contents of the register X introduced into the ACC are added to the numerical value N'fr, and the result of n is obtained in the ACC. P3... By exchanging the sum found in ACC and the contents of register
Execute e2. (Type 3) M+ +N=Mz wa■ Pl...Specify the area to be processed in the first memory using the file address mB and digit address nc. P2... ACC the contents of the memory specified by Pl.
In order to return the addition result to the second memory, the file address m of the second memory is specified. P3... Specify the numerical value N to be added with the operand, and
The contents of the memory introduced into the CC are added to the numerical value N, and the result is obtained from the ACC. P,...The second value specified by P2 is the sum obtained for ACC.
Converts the contents of the memory of , and executes Type 8. (Type 4) Ml-N→M+ Pl...Memory file address to be processed mB
and digit address nC. P2...Subtraction is a method of adding the complement of the subtracted number to the minuend,
Since there is no F digit, there is no borrow and F/FC is set. P3...Introduce a subtractive number N to ACC. Pc: In the process of taking the 15's complement of the subtracted number, the complement is found in ACC. P5...If there is no borrow from the lower digits, subtraction is replaced by a process of adding the 16's complement of the subtracted number and the subtracted. Let the state with no borrow be C=t, and ACC4-C+M→AC
CK and pure binary subtraction is performed. P6: Swap ACC and memory in order to return the difference found in P5 to the same memory. (TYpe 5) M+ N'M2゛P6
...In order to introduce the difference found in P into the second memory, the file address m and digit address nc of the second memory are specified. P7...The difference data determined by ACC is transferred to the second memory specified in P6 by exchange. (Type 6) WaPl...Specify the address of the temporary save memory at P5 using file address mB and digit address n (.P2...Subtraction is a method of adding the complement of the subtracted number to the called number,
Since there is no lower digit, the pollo number is set (F, 11-C is set. P3... Introduce the subtrahend N to ACC. P,... In the process of taking the 15's complement of the subtrahend, the complement is found in ACC. P5... Introduce the contents of the memory VcAcc specified by Pl in preparation for calculation with the contents of register X. P6... Transfer the contents of register X in exchange with ACC. When the processing is finished, the memory contains the 15's complement of the subtraction number, and ACC contains the contents of X. Pl...ACC) Ml-C is the processing equivalent to X-H, and is the actual result of subtraction in binary. is found in ACC. P8...The contents of ACC and the contents of X are exchanged, the value of X-N is transferred to X, and Type 6 processing is completed. (Type 7) N-Ml -18 (1 ■ PI...: Memory file address m to be processed
B and the digit address net-specify. P2...1゛digit is subtracted, and the complement of the subtrahend is added to the minuend, so °F4 Cf is used. P3...Introduce the minuend to ACC. P4...Exchange memory contents (subtraction) and ACC,
Also, in preparation for the processing of P7, the memory file address is m.
Leave as B. P5...The complement of CC is determined by the process of taking the 15's complement of the subtracted number of ACC. P6...If there is no pollo from the r digit, subtraction is replaced by a process of adding the 16's complement of the subtrahend and the minuend. Assuming that C=1 in a state where there is no pollo, NM is substantially performed with ACC+-C)M, and the difference is obtained from ACC. Pl... Since the memory file address remains mH as it is in P4, the difference in ACC is stored in the original memory and Type 7 is completed. (Type 8) N-Ml → M2 Pl... File address of processing memory mB
and designate the decided address nc. Pl...The content corresponding to the subtrahend specified by Pl is AC
Introduce it to C. In preparation for processing P5, specify the file address m in the second memory. P3...The complement of ACC is determined by the process of taking the 15's complement of the subtracted number of ACC. Pl... The contents of the operand are set to the minuend plus 1. This subtraction is for one digit, and is replaced by the process of adding the complement of the subtracted number and the subtracted number. Typical complement addition in the absence of borrows is
As in e7, <ACC+C+M, and it is processed as C=1. Since there is no C in the ADI instruction, ACC
Process by performing +-1. By this, Ty of N-M
The subtraction result of pe8 is found in ACC. P5...Transfers the difference data obtained by Pl to the second memory with 1 degree specified by Pl. (Type 9) M total 1-M P, ... (when M+-1) ACC is binary number 0001 (
-1) will be introduced. p,...(When M-1) Binary number 1111 (=
15) will be introduced. Pl...Memory file address to be processed m8
and digit address nc. P3: Adds the content of the memory designated by Pl and the content introduced in ACC by Pl or P, and introduces the sum into ACC. In the case of Pl, the ACC becomes 11, and in the case of Pl, the ACC becomes substantially 1. Pl...The memory obtains the result requested by ACC and completes the transfer LType9. (Type) Since there is no carry processing for
At the same time, m of the second memory is added to the file address in preparation for addition with the contents of the second memory at Pl.
Specify it as B. Pl... Add 6 to the contents of the desired digit of the first memory introduced into ACC, and add lO to the next digit when adding in P5.
Used to determine whether or not to proceed. P5...Pl f 1st memory 6 correction is required for ACC, the contents of this ACC and the contents of the same digit in the second memory specified in P3 are added in pure binary, and the contents are added to ACC again. Introduce. The fourth of this pure binary addition
If a digit is found in the addition of the bit, skip P6 and proceed to P7. The fact that the addition of the 4th bit results in a carry is,
This means that there was a 1o decimal carry. P6...When the decimal digit does not appear in the addition of P5, P
, the 6 added in steps is subtracted in this step to return it to its original value. Adding 10 is the same as subtracting 6. Pl...Transfers the 10 digit sum found in ACC to the second memory by exchanging it, increases the digit address in preparation for addition of the next digit, and then transfers the first memory to the file address. Specified in mA1. I'll leave it there. By predetermining the final digit to be added as nl, when all seven digits in the first and second memories have been added, B L = nl.
Therefore, the next P8 is skipped and the Type 1 processing is completed. P8...Specify program address P3 and press BL-
The commands P3 to P7 are repeated until nl is reached, and the decimal addition is performed one digit at a time. (Type 2) X-W-+XPl-...The first digit of the first memory to be processed is specified by the file address mA and digit address nE. P2...Subtraction is a method of adding the complement of the subtracted number to the minuend,
In the subtraction of the first digit, there is no polling process from the lower digits, so F4C is set. P3... Introduces the contents of the desired digit subtraction in the first memory into the ACC, and specifies the second memory file address mB in preparation for processing with the second memory at P5 + P7. P4: Processing for taking the 15's complement of the subtracted number. The 15's complement is found in ACC. P5... If there is no pollo from the lower digits, subtraction is replaced by adding the 16's complement of the subtrahend and the minuend, and if there is a pollo from the F digit, it is replaced by adding the 15's complement of the subtrahend and the minuend. Replaced. Let C = 1 for the state without pollo, and A
A pure 2 quasi subtraction is executed in CC+-C+-M-+ACC. The fact that a carry occurs as a result of executing this ADC8K instruction means that no pollo occurred during subtraction, so
Skip P6 and proceed to P7. Note that since the addition here is performed with the second memory designated by P3, it is essentially the second memory and the first memory. P6...If a carry does not occur with the ADC5K instruction in P5, the result is determined in hexadecimal, so subtract 6 (equivalent to adding 10) to return it to decimal.P7...ACC Transfer the difference between the second memory and the first memory found by exchanging it with the contents of the second memory.In preparation for subtracting the next digit, increase the digit address, and then specify the first memory with the file address mA. The final digit to be subtracted is nl beforehand.
By determining BL=nl when the subtraction between the second memory and the first memory is completed for all digits, the next P8 is skipped and the Type 2 processing is completed. P8...Specify program address P3 and set BL=n
The commands P3 to P7 are repeated until , and the decimal subtraction is performed digit by digit. ft. (Type) Right shift P, ... s - t memory file address m
and digit address nA. When P2...Q is introduced into ACC and shifted to the right,
Prepare to put 0 in the upper digit. do. P3...Exchanges the contents of the memory with ACC, lowers the digit address, and specifies the first digit of l. The memory file address does not change in mA. Since it returns to P3 again via the next P4, it means repeating XD. The 0 you put in ACC in P2 is the first ACC
-M enters the most significant digit of the memory, and the contents originally in the most significant digit enter ACC. Digit address is down at P3, returns to P3 via P4 and executes XD 1. At this time, since one digit lower than the most significant digit is specified, the content of the original most significant digit contained in the ACC is transferred to the l digit y F position. At this time, the contents of 1 digit F from the most significant one are transferred to ACC. By predetermining the least significant digit as n2, if the above transfer is repeated up to the least significant digit, BL=n2 is satisfied and P. Skip and finish. That is, the contents of each digit are transferred to the F-th digit and TYpe 1 is executed. P4...Return to P3 to repeat XD of P with the switch where BL=V. (Type 2) Left shift Pl...File address m of processing swipe memory
and @r-place digit nE. Introduce P2...0 to ACC, shift to the left, and prepare to insert 0 into the least significant digit. P3・-'・A When CC and memory contents are exchanged, J
(Increments the digit address and specifies the upper l digit.The memory file address is not changed with m.It returns to P3 again via the next P4, which means repeating XI.The 0 that was entered in ACC in P2 is placed in the least significant digit of memory at the first ACC-M, and the contents that were in the original least significant digit are placed in ACC.P3
The digit address is uploaded in ``r'' via P4.
When returning to step 3- and executing XI, since the lowest digit -F is specified, the content of the original lowest digit contained in the ACC is transferred to the 1 digit H. At this time, the contents of one digit higher than the lowest order are transferred to ACC. By predetermining the most significant digit as nl, repeating the above transfer up to the most significant digit 7) satisfies BL=nl and ends the process by skipping P4. That is, the contents are transferred to the upper digit 7) for each digit, and Type 2 is executed. P4...Return to P3 to repeat XI of P3 until BL=V. (Type]) *P, . . . Specify the area of memory to be processed (digit y) with the file address mB and digit address nc. P2...Pl Introduce 1 to the desired digit N in the memory digits and execute Type I. ("Type2) P,... Specify the digit of the memory area to be processed using the file address mB and digit address nc. P2... Desired pix in the memory digit specified by Pl) For NK Introduce 0 [2, Execute Type 2. (Type 1) W ■ Pl...Specify the file address mB and digital store address n where the desired conditional F/1 pinto exists. P2...If the content of the bit specified by N (corresponding to the desired conditional F4) in the memory area specified by P is 1, skip Pl, proceed to P4, and execute operation OP. .If the content of the desired bit is 00, proceed to the next step P3. P, ... Conditional F/F based on the judgment at P2
is set to 0, and the program step is set to P to execute operation OP2. Specify K. ■ P,...The memory area that contains the content to be judged is set to the file address and digital address n.
Specify with. P2...Introduces the memory contents specified by Pl into ACC. P3...ACC contents and predetermined numerical value N
If they are equal, skip P4, proceed to P5, and execute operation OPr. If the contents of ACC and N are not equal, proceed to P. P, . . . Specifies program address (step) Pn and jumps to Pn. Opera recon OP at Pn,
Execute. Pl...Specify the memory area to be judged with the file address mB, and set the first digit address with nE.
Specify with. P2...Introduce the numerical value N to be compared into ACC. P3: Compare the comparison value N of ACC with the contents of desired digit (4) in the desired area of memory (11). If they match, skip P4 to compare the following digits and P
Proceed to step 5. If they do not match, proceed to P. If there is a mismatch in P, . . . P3, the program address (step) is designated as Pn and jump is made to immediately execute the operation. P5...Increments the digit address by adding 1 to it. This process is for sequentially judging multiple digits in memory. By predetermining the final digit address of the memory to be changed as (V), the above comparison is repeated for a desired number of digits. If there is a disagreement on the way! ! When the number reaches 13, the operation oP2 is executed via P4, but if there is a match until BL=V and there are 7 consecutive matches, P6 is skipped and the process proceeds to P7, where the operation op is executed. P7...When a match continues at P5, return to P3 and repeat the judgment. change. Pl...Specifies the file address m8 and digit address n of the memory to be judged. P2...Introduces the memory contents specified by Pl into ACC. P3...If the numerical value to be compared with the memory contents is N, specify the numerical value 16-N with an operand, add the contents and the memory contents of ACC, and obtain ACC. In this addition, the 4th bit carry comes out, which means 2
This means that the base addition result exceeds 16. In other words, M+(16-, N') > 16,
This means that M>N is not satisfied, so proceed to P4. P,...-When it is not a VAN, specify the program address to Pn in this sudenbu and jump ° (7, Execute operation OP2 with Pn. Change (step). ■ Pl... Memory file to be judged Specify address mB and digit address nc. P2... Introduce the memory contents specified by Pl into ACC. P3... Set the numerical value to be compared with the memory contents to N3.
Specify the numerical value 15-N as an operand, and write its contents and A
Add the memory contents of CC and obtain ACC. The fact that a carry appears in the fourth bit in this addition means that the binary addition result exceeds 16. That is, M+-(15
-N)>16, which means M>N'+-
1, that is, M>N. In this case, this instruction skips P, proceeds to P5, and executes operation OP. If there is no carry, it is not a MAN and the player moves to P. P,...M) If not N, specify the program address (step) to Pn at this step and jump to P.
Operation OP2 is executed at n. Q41 Display the contents of the desired area of memory. (Type 1) Pl...Inputs the focus number n1 of W to ACC to reset the entire contents of the buffer register W that generates a digit selection signal for time-divisionally displaying the display. P2... After shifting the entire contents of register W by 1 bit to the right,
Input 0 to the first bit. The entire contents of W are reset by repeating this through P4 until C4-1 is reached at P3. P3... By setting the operand IA to 1111, AC÷1111 is performed, and ACC-1 is essentially performed. Since ACCK n 1 is entered in Pl, by repeating this number of times, the next 111 with ACC = 0
The 4th bit is used only when adding with 1! J-C47310
Therefore, proceed to P only in this case, and proceed to P5 at other times. P4...4th bit carry C4 at AC+1111
- When 〇, all contents of W are set to 0 [7' (Thus, the preprocessing is completed, and the first address P6 of the display step of the memory is
jump. P5... 4th bit carry C at ACC 71111
At 4-1, the process of setting all the contents of W to 0 has not yet been completed, so return to P2 and repeat the process of setting W to 0. P6... Specify the first digit with file address mA and digit address nA. P7: After shifting the contents fr of the register W that generates the display digit selection signal to the right by 1 bit, 1 is put in the first bit. This prepares for supplying a digit selection signal to the first digit display. Pa... AC the contents of the desired area of the specified stolen memory.
Enter in C. Memory file address does not change mA
It is. Also, in preparation for processing the next digit, the decend address is down. P9...Transfers the contents of the memory stored in ACC to the output buffer and far register F. The contents of register F are input to segment decoder SD, which generates a segment display signal. PIQ...The contents of register W are output as an external display signal and 1.
In order to output it, put 1 in the conditional F/FNP and set it to the set state. With this, the memory contents processed by P are displayed on the first digit display. Pl+...Input count initial value n2 for determining display time for one digit to ACC. P1□...substantially pacifies ACC-1 in the same way as P3. When ACC becomes O, skip to PI3, and when the content of ACC is not O (when c4=1), skip to -Pl4 and repeat this process. PI3... The desired display time is processed by counting the content of ACC in P1□, and when the counting is finished, it jumps to P15 via ph3. This count time becomes the one-digit display time. Pl4: When the desired display time has elapsed, skip P1□ to Pl3, proceed to Pl4, jump to Pl2 again from 1, and repeat this process. Pl5...Resets NP and stops supplying the digit selection signal to the display. Next, until NP is set again in PIO, the overlap display prevention low by the adjacent digit signal of the display is applied. Pl6...In preparation for displaying the next digit, shift the V register W by 1 bit to the right and put 0 in the 1st bit, essentially shifting the 1 bit F digit entered in P7) L, Prepare for next digit selection. Plr: Checks whether the last digit of the memory to be displayed has been completed, and since BL-1 has been done in the processing of Pa, it is checked whether the value nE of the final digit-1 has been reached. Pl8...Pa when the final digit has not arrived
Return to , and display the next digit. Pl9...For example, if the flags F/F and FA are used as display termination conditions, FA=1, skipping P2O 17 and ending the series of display processing. P2O...If PIQ is FA-0, @1 digital again.
To repeat the process of displaying 7 bruises and 0, jump to Pa'
Click. (Type 2) Pl... In order to reset the entire contents of the buffer register W that generates the digit selection signal for time-divisionally displaying the display, the number of bits of W is n1. Input into ACC. P2... After shifting the entire contents of register W by 1 bit to the right,
Input all 0s to the first bit. By repeating this through P4 f: until c and -i are reached at P3, the entire contents of W are reset and l-. P3...By setting the operand IA to 1111, AC)+111 is performed, which is essentially ACC-J'? conduct. P, TEACCK n + is inserted, so this number of times (the 4th via is only when adding with the next 1111 which becomes ACC = 0), the carrier IJ-C4 becomes 0, so this Proceed to P4 only when, otherwise P5
Heskidde. P4...ACC++ When the fourth bit carry C,=Q in 111, all contents of W have been set to 0, so the preprocessing is completed and the display jumps to the first address P6 of the memory display depth. P5...4th bit carry C at ACC+1111
If it is 1-1, the process of setting all the contents of W to 0 has not yet been completed, so the process returns to P2 and repeats the process of setting W to 0. P6--Specify the upper 4 bits of the first digit of the memory area containing the content to be displayed using the file address mA and digit address nA. P7...AC the contents of the desired area of the specified memory
Enter in C. Memory file address does not change mA
It is. Also, lower the digit address and specify the lower 4 bits. P8: Transfers the contents of ACC, ie, the upper 4 bits, to temporary register X. P... AC the contents of the desired area of the specified memory.
Enter in C. Memory file address does not change mA
It is. Also, lower the digit address and specify the upper 4 bits of the next digit. PIG... ACC contents to stack register SA,
The contents of temporary register X are transferred to stack register sx
to be introduced. po: After shifting the contents of the register W that generates the display digit selection signal to the right by 1 bit, 1 is placed in the first bit. This prepares for supplying the first digit selection signal. PI2... The contents of the register W are displayed as an external display signal and 1.
conditioner for output) v Put 1 in F/FN P to set state. With this, the memory contents processed by PIG are displayed on the first digit display. PI3: Input the count initial value n2 to determine the display time for one digit into ACC. PI3: Performs ACC-1 substantially in the same way as P3. When ACC becomes 0, it goes to PI3, when ACC~0 (
When C4=1), skip to Plg and repeat this process. P... Desired display time is P, 4 ACC content color...
When the count is completed in step 17, the count jumps to P17 via PI3. This count time becomes the one-digit display time. Plg...If the desired display time has elapsed, skip Plg from PI4, proceed to Plg, jump to PI3 again E2, and repeat this process. PI7...N is reset to stop supplying the digit selection signal to the display. Next, until N is sent again at PIO, the adjacent digit signals on the display are used to prevent overlapping display. Plg...In preparation for displaying the next digit, shift register W to the right by t bits and put 0 in the first bit, effectively making it 1.
Shift the 1 input in P7 to the lower bit bit. PIG...Checks whether the last digit of the memory to be displayed has been completed, and since B and -1 have been done in the process of P9, it is checked whether the value of the last digit -1 has reached rrEVC. P2O...P7 when the final digit has not arrived
Return to , and display the next digit. ζIυ to determine the type of suppressed key switch
P, □ P1~pH+... (This is the display heat expansion explained in 141. PI9... After displaying the contents of all the digits of register W, set the flag F/F F C, and turn on the key signal I. ,~
1. Set all to 1. P2O...If any of the keys connected to the key KN+ is pressed, PB. Jump to. P22 to P27...For each of the keys KN2 to KF2, judge which of the connected keys has been pressed, and if it is pressed and there is no dispute, skip the next step 1. I'm leaving. If pressed, jump to P30. P28...When no key is pressed, F
4-Reset the FC 2 and finish the key suppression check. P2O...P6 jump and continue displaying again. P.B. . . . In the step that comes when the key is pressed, the memory digit address is set to the first state nl in order to generate the first key strobe signal I0. PI3...key human power KN, 1st key strobe r
Judge 1 whether No. ii ■1 was input. , if not input, skip to P33. P32...Key human power KN1ρ When the first key strobe signal ■1 is input, the type of key is determined, the control jumps to PA, and the control corresponding to the determined key is thereafter performed. After ending the key control R1, the program jumps directly to 1riP and starts displaying. (Pz'd, P l
Example of steps to jump to) P33~Pss・
...First key strobe signal 1. If the desired key is pressed, jump to PB-PD and perform control corresponding to that key. P3O: When the key connected to the first key strobe signal I is not pressed, the memory digit address can be increased to generate the second key strobe signal. P41~... Generates a desired key strobe signal, and sequentially judges KN, ~KF2, and determines the type of pressed Ff key [-1 Control # for the pressed key.
Jump to the desired step to complete. PA~... Control for the first key Px...
- After the first key control is completed, return to P1 and resume display. The above is an explanation of the main processing processes of the CPU device. Next, an example of the display operation of a computer that executes the display method of the present invention will be explained based on the flowchart of FIG. In the figure, this is the step of executing the operations programmed by the nl operators. n2 is a step for determining whether the state is in the Hart state, and if the state is not in the Hart state, nl n2 is repeatedly executed. This
The current state is a state in which calculations are temporarily stopped until data is input at a step in which data is input from the outside during program execution. If you are in a healed state, n
Proceed as 2 → n3, and set the value N1 of a certain − sect to the counter CO.
Enter. Counter CO is constituted by a part of RAM. Then, in step n4, the calculation result (intermediate result) 5
Displays the content MX. Counter c at n5. It is determined whether the contents of the counter co are 0 or not, and if CON0, the process proceeds to step n6 and 1 is subtracted from the contents of the counter co. That is, n4→n5→n6→n4→n5→... is N
++Repeat 1 time 12, display MX for a certain period of time. (For example, for 5 seconds) If the contents of counter co become 0 after that, n5
→N7, and increment the counter RK:1. Counter R is constructed as part of the RAM. It is assumed that the counter R has been reset in advance and is set to ``Off.'' R stores the collection of the Hart state.Next, in n8, the suppress code cS is set to the character memory MC.
is input. Character memory M C1dRA M
This is a register in one area, and one character is stored as an 8-bit code. Also, the sagress code C5 is a code for not displaying anything on the display section, for example, 111.
Let it be 1111 bits. In step n, the code for TE°j is stored in the electrical phase of the character memory MC.nl(l
Then, the contents of the program counter PL in the ROM plus 1 are stored in the 10-gram stack register SP. (Refer to instruction code 454) This is a return instruction RIT (instruction code &5
5) to specify the return destination. Next, proceed to step n1° → n26, and store a constant value N2 in the ROM.
input to the counter CO inside. The contents of the character memory MC are displayed at n27. At step 12g, it is determined whether the contents of the counter CO have become 0 or not, and if CON2, the process advances to step 129, where 1 is subtracted from the contents of the counter CO. At step 130, it is determined whether or not there is key power, and if the key is not operated, proceed to n3o-+n27.
Repeat once and display for a certain period of time. After displaying for a certain period of time, n21
1→n31, and the contents of the character memory MC are shifted to the displayed telephone public figure. In step n32, it is determined whether the conditional F/FA (part of RAM) is in a cassette state or a set state. In F/FA, after all the instruction data is recorded in character memory MC, it is cented at 135, and -data (Fig. 2(b) to (
f) Determine whether or not the display of item 2) has ended. In this case, since F/FA is in the reset state, n32 →
Step n33 is followed by a return instruction (RIT) to proceed to step nil. ntt's step °kennlQ's TML &
This step corresponds to the contents of the program counter P of the ROM stored by the command. To this monk, nQ″n+o″
nza-n2y″n2s″n2y-n3o″→n27→
n2g ”' → n3t → na2 → n3a, Figure 2 (b)
Finish displaying "D" as in
6→n27″'n28°1211″030″n27”
n2s''n31-n32→n33, "day" is displayed as shown in FIG. 2(c). From then on, % n 15″n 16″n 26″n'2
7 n 28°n29°n3G°n27-128- n
1 data is displayed at 3t -n32°n33. After that, proceed from n33 to n+7'', remember the step to return with RTT (return command), and proceed to n17'n311.
Determine the contents of counter R. If R=1, that is, in the initial Hart state, R=1 at n7, proceed from n38 to n44, and character memo! J-
'Store the FAI code in the first digit of the VC. Then, the process proceeds as n44→n45→n18, and after storing step n19, which is returned by a return command at n18, the process proceeds to step n26. Therefore, similarly n44→n45→n1g″n26
″nzy″n2g″n29″n30″n27″n 28
→n31→n3□→n33 displays "data A". As described above, by shifting the display contents stored in the character memory, storing the newly displayed character in the first digit, and displaying the contents of the character memory, the contents of the character memory can be displayed. ) is displayed. Then, as shown in FIG. 2(f), after the display is finished, the process proceeds to step n35 by the return command in n33. In n35, the conditional F/FA is set, and in 13g, the suppression code is placed in the first digit of the character memory MC. C8 is stored. This suppression code C8 is used to distinguish between display contents and display contents. In step n37, it is determined whether all the digits in the character memory MC store the suppress code C8 and are names. (MCFC8) This is so that the display circulates, a certain display is shifted, and after it has completely disappeared from the edge of the display section, the beginning of the same display content begins to be displayed. In this case, all digits are suppressed codes, and the sequence proceeds from n, 7 to n26, and is displayed as shown in FIG. 2(g). After that, the content of the character memory is shifted in n31, and the suppress code is stored in n36, so that the displayed content disappears from the left end of the display section, and as shown in Figure 2 (i), all digits of the character memory are filled with the suppress code. The display advances to 7, 36, 37-n9, and the display is repeated, that is, the instruction ``Denitor A filet-yo'' is repeated. Here, since the operator has programmed the calculation to be performed in step n, he inputs the numerical value corresponding to data A using the keys. Therefore, it is determined in step 130 that there is key manpower, and the process returns to n 30-+11.
Calculations are started in nl based on the numerical values entered manually. □ After that, when it becomes Hart state again, it progresses from n2 to n3,
n in the same way as in the first Hart state. --ns-jl At 5-n4, the result of the calculation (intermediate result) is displayed for a certain period of time, and at n7, 1 is added to the counter R. In this case, JR=2. From then on, at 0171, the process proceeds in the same way as the first Halt state, but since R=2, n
17→n38"'139→'143, and in order to indicate that the next data to be input is B, the code for B is stored in the character memory MC at n43. Therefore, in the second Halt state, " The display will be "Data B filet." Similarly, when the third Hart state is reached, [Data C File Yo J J J When the dth Hart state is entered, "Data D File Yo J" is displayed. Figure 7 shows the subroutine W in Figure 6. The flowchart for executing I≧4 is shown [7]. At step n, the conditional F/B (part of RAM) is reset, and at nb, the contents of the character memory MC are reset to 4 bits. It is shifted to the left. At nc, the flip-flop B is determined and the process proceeds to nd. At nd, F7FB is set, and at nb, the character memory MC is again shifted to the left by 4 bits, and this subroutine ends with the determination of the next FlB. Character memory VC
The code Id of one character is stored at the 8th point, and a shift of one character is performed by performing a 4-bit shift of 21. Each process in the flowcharts of FIGS. 6 and 7 is described above.
- The processing can be executed based on the contents of each processing list of the CPU device. Here, Table 3 is a table showing the relationship between the processing contents of the CPU device and each step for executing the flowchart shown in FIG. ~09'' respectively. As shown in Table 3, each step in the flowchart of FIG. 6 is achieved by executing the processing content corresponding to the processing list number of the CPU device shown in Table 3. In addition, Sue
Te7pu nl+ nlo+ n12+”+4+n16
A'n18+n20+n224n24+n33+n45
This can be easily understood from the explanation of the CPU device mentioned above. Next, the relationship between each step and the processing list number of the CPU device when performing the left shift of the memory character MC in FIG. 7 is shown in the table below. Table 4 By processing each step as described above, the @ operation of MC left shift can be executed. As described above, the present invention allows display control of an electronic calculator or the like to be performed using a CPU, a device that decodes and executes instruction commands. According to the present invention, when a program enters a halt state in the middle of executing a program, the data to be input is displayed in a running display [7] The operator can smoothly input data based on the instructions; The contents can be changed depending on the internal processing state of the computer. Also,
By displaying only the instruction contents in a running manner, it is possible to display more display contents than the display capacity of the display body.

[Brief explanation of drawings]

Figure 1 is an external view showing an example of a program computer equipped with the display method of the present invention, Figure 2 is a diagram for explaining the display state of the computer, and Figure 3 is an example showing the main parts of the computer. FIG. 4 is a logic circuit diagram of an example of the CPU device of the computer, including FIGS. 4A to 4D. Fig. 5 is a diagram illustrating a circuit equivalent to the CPU device in Fig. 4, Fig. 6 is a flowchart for explaining the display method of the computer, and Fig. 7 is an illustration of the left shift operation of the MC. FIG. In the figure, 1: Display section, 2: Display section, 3: Key human power device, 4
: Central processing unit (CPU), 5: Gear arctor generator (CRG'), 6: Display body, 7: Digit selection signal, 8:
Segment signal, 'Ri'u-: Random access
Memory, ROM: Read-only memory, AC
C: Accumulator. Agent: Patent attorney Aihiko Fuku (2 people) Ah.
tθ da (h) second flash

Claims (1)

[Claims] 1. In an electronic device that is equipped with a display that can display multiple characters and has a program calculation function, when a halt state occurs during program execution, the content of the character specified by the next data to be input is displayed running. A display method for an electronic device, characterized in that the content of the running displayed character can be varied depending on the internal state of the computer.